Journal of Circuits, Systems and Computers

In this paper, Ultra-Wideband (UWB) filters at 6–18GHz are designed that can reduce undesired frequency responses at lower and upper frequency bands to less than $-$20dB. Arbitrary load impedances are considered in the design of these filters. The structure of these filters is the combination of microstrip band-pass filters and Defected Ground Structures (DGSs) with multiple sections. The optimum circuit dimensions are calculated using a computer code which implements the Least Mean Squares (LMS) optimization method. Two design examples are included to illustrate this method. In these examples, eight-section DGS structures are employed to eliminate the unwanted upper frequency band responses. To ensure the correct performance of the designed filters, they are analyzed using full-wave methods and fabrication and the results of the measurement or full-wave analysis shows good agreement with the results of the computer code and the circuit model simulations.

In this study, a new current-mode fractional-order universal filter is presented by using multi mode second generation current controlled current conveyors (MO-CCCII). The circuit consists of two resistors and grounded capacitors with only three MO-CCCII. This is accomplished with a fractional-order capacitor, also known as a stationary phase element, to form a fractional-order filter. The value of this capacitor depends only on the fractional-order $\alpha (0<\alpha <1)$. The proposed filter is designed as fractional $(1+\alpha )=1.5$, 1.8 and 1.9 order. The fractional-order capacitor is obtained using the Foster-I $RC$ network circuit. The filter is simulated with BJT-based MO-CCCII using PSPICE simulation program for the filter to verify the theory and to show the performance of it. The fractional-order universal filter outputs are provided the desired stop band attenuation and more precise control of attenuation slope. Through the fractional-order parameter, it is revealed that the filter designer can fully meet the requirements of the filter. It also offers design flexibility since the frequencies of interest depend not only on circuit components but also on fractional-order parameters.

Flexible ultra-wideband (UWB) antenna arrays with band notching characteristics are proposed in this work. A new wideband and high-isolation Wilkinson power divider (WPD) is designed to construct the feed systems of the UWB antenna arrays. The proposed WPD is achieved by introducing a significant modification to the conventional WPD and the new one is composed of four isolation stages. Multiple stages helped to achieve wideband from 2GHz to more than 12GHz with high isolation characteristics of more than 20dB and insertion losses around 3.3dB. The designed WPD is then applied to feed two UWB monopole antenna arrays which offer a notched band centered at 5.5GHz to reject interference from wireless local area network (WLAN) system and can be integrated with curved surfaces. To verify the performance of the proposed structure, two array configurations are practically fabricated and measured. The results show that both the arrays have UWB operational bandwidth (3.5–11.8GHz for $1\times 2$ array and 3.6–12GHz for $1\times 4$ array) that includes the UWB spectrum. Attractive agreement between simulation and measurement results is obtained. Furthermore, the bending test is carried out on the $1\times 4$ array showing the good performance of the proposed system when installed on curved surfaces for different bent angles.

Power system often experiences the problem of low-frequency electromechanical oscillations which leads the system to unstable condition. The problem can be corrected by implementing power system stabilizers (PSSs) in the excitation control system of alternator. This paper provides a novel and efficient approach to design an Improved Grasshopper Optimization Algorithm (IGOA)-based dual-input controller to damp the inter-area-mode power system oscillations. A three-fold optimization criterion has been formulated to calculate the optimum values of the controllers required for power system stability. The damping performance of the proposed controller is compared with conventional PSS and genetic algorithm-based controllers to validate the better performance of the proposed IGOA-based controller under various system loading conditions and disturbances.

The objective of the research work is to analyze and validate health records and securing the personal information of patients is a challenging issue in health records mining. The risk prediction task was formulated with the label Cause of Death (COD) as a multi-class classification issue, which views health-related death as the “biggest risk.” This unlabeled data particularly describes the health conditions of the participants during the health examinations. It can differ tremendously between healthy and highly ill. Besides, the problems of distributed secure data management over privacy-preserving are considered. The proposed health record mining is in the following stages. In the initial stage, effective features such as fisher score, Pearson correlation, and information gain is calculated from the health records of the patient. Then, the average values are calculated for the extracted features. In the second stage, feature selection is performed from the average features by applying the Euclidean distance measure. The chosen features are clustered in the third stage using distance adaptive fuzzy c-means clustering algorithm (DAFCM). In the fourth stage, an entropy-based graph is constructed for the classification of data and it categorizes the patient’s record. At the last stage, for security, privacy preservation is applied to the personal information of the patient. This performance is matched against the existing methods and it gives better performance than the existing ones.

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18$\mu$m standard RF CMOS process for 6–16GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The $-3$dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The $-3$dB gain bandwidth of the proposed LNA is 10GHz, while the maximum power gain of 13.1dB is attained. With this structure, minimum NF of 4.6dB and noise flatness of 1dB in the whole bandwidth can be achieved. The input impedance is matched, and S${}_{11}$ is lower than $-$10 dB. With the proposed linearized LNA, the average IIP${}_3\mathrm{\text{ of}}+0.5$dBm is gained, while it occupies 1051.7$\mu \mathrm{\text{m}}\times 749.7\mu$m die area.

In recent years, underwater wireless sensor networks (UWSNs) have been widely applied to aquatic and military applications. Network survivability is an essential attribute to be considered in UWSN circumstance and various stratifications like node survivability, connectivity and rapid fault node detection and recovery. However, efficient and accurate fault tolerance mechanisms are required to prolong the network survivability in UWSN. In this research work, the energy-efficient fault detection and recovery management (EFRM) approach is proposed for the UWSN with relatively better network survivability. The hidden Poisson Markov model has been incorporated in EFRM to achieve efficient fault detection throughout the whole network. Thereafter, the recovered node can be selected by using the analytical network process model which facilitates to recover the larger number of nodes in the damaged region. The simulation results manifest that when the fault probability is 40%, the detection accuracy of the proposed EFRM is over 99%, and the false positive rate is below 2%. The detection accuracy is improved by up to 12% when compared with the existing state-of-the-art schemes.

Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ($\mathrm{\text{Design}}-1$ and $\mathrm{\text{Design}}-2$) have Error Distance (ED) of $\pm 1$ and Error Rate (ER) of 25%. The proposed $\mathrm{\text{Design}}-1$ and $\mathrm{\text{Design}}-2$ are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement $8\times 8$ Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

Robust head pose estimation significantly improves the performance of applications related to face analysis in Cyber-Physical Systems (CPS) such as driving assistance and expression recognition. However, there exist two main challenges in this issue, i.e., the large pose variations and the property of inhomogeneous facial feature space. Head pose in large variations makes the distinguished facial features, such as nose or lips, invisible, especially in extreme cases. Additionally, features extracted from a head do not change in a stationary manner with respect to the head pose, which results in an inhomogeneous feature space. To deal with the above problems, we propose an end-to-end framework to estimate the head pose from a single depth image. To be specific, the PointNet network is adopted to automatically select distinguished facial feature points from visible surface of a head and to extract discriminative features. The Deep Regression Forest is utilized to handle the nonstationary property of the facial feature space and to learn the head pose distributions. Experimental results show that our proposed method achieves the state-of-the-art performance on the Biwi Kinect Head Pose Dataset, the Pandora Dataset and the ICT-3DHP Dataset.

As one of the workload characteristics, the anomaly behaviors in real workload have been recognized as a critical requirement for file system design. In this paper, a set of traces collected from typically realistic file system have been analyzed. The correlation study of I/O request inter-arrival times shows that it is necessary to examine the self-similarity in file system workload. Then the phenomenon of self-similarity which had been initially observed in network and disk I/O workload has also been visually and statistically observed in file system workload. In addition, we implement an I/O series generator in which the inputs are the measured properties of the available trace data. Experimental results show that this model can accurately emulate the complex access arrival behaviors of real file systems, particularly the heavy-tail characteristics.

The main factors that affect the performance of residue number system (RNS) are speed and hardware complexity of the residue-to-binary converter. In this paper, two efficient reverse converters are proposed for the moduli sets $\{2^{2n-1}-1,2^n-1,2^n+1,2^n\}$ and $\{2^{2n-1}-1,2^n-1,2^n+1,2^{2n-1}\}$ based on two-level approach. In the first level, a reverse converter is implemented based on new Chinese remainder theorem-I for the moduli set $\{2^{2n-1}-1,2^n-1,2^n+1\}$. The fourth modulus is joined in the second level for each converter and only simple binary adders are used in this level. The architecture of novel circuits mainly consists of simple adders thus leading to implementing efficient converters. To have a fair comparison, both unit gate model and simulation are used. The proposed converters and the recently represented converters have been implemented on Xilinx ISE 13.1 field-programmable gate array (FPGA) simulator to derive area and delay that are measured for the various ranges up to 256 bits. The experimental results show that the proposed converters have lower area–time complexity comparing to the state-of-the-art converter for similar moduli sets.

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the $4\times 8$ two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3dB SFDR, enabling to correct the SFDR by more than 23.6dB compared with the structure without DEM.

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely $|V_{\mathrm{\text{GS}}}|+2|V_{\mathrm{\text{dsat}}}|$. Fabricated on a 0.18$\mu$m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves $-72$dB total harmonic distortion $(\mathrm{\text{THD}})+\mathrm{\text{noise}}(N)$ with a loudspeaker load of 100ohm while operating from a 1.2V supply and being subject to a 1kHz sinusoidal input.

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the $L$ and $C$ by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13$\mu$m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34GHz. The results are consistent with the delay analysis based on the proposed IL model.

This paper proposes a switching load technique to improve the mismatch at outputs of the transformer-based single pole double throw (SPDT) switch, thus improving the insertion loss (IL) performance. A switch is introduced as the load of the primary inductor of the conventional transformer-based SPDT switch to improve the IL performance in transmission and receiving operation modes. A transformer-based SPDT switch is implemented with the switching load technique in TSMC 40nm CMOS technology. The transformer which has a symmetrical shape is implemented with the thick metal for low IL propose. The simulated results show that the proposed SPDT switch achieves a minimum insertion loss of 1.64dB and the IL is better than 2.2dB across the range from 24 to 35GHz. The proposed SPDT switch occupies a core area of $140\times 225\mu$m² and the return losses are better than $-11$dB at 24–35GHz.

Electrical neural activity monitoring and recording will increase our understanding of how the human brain works. Tracking mechanisms of neural activity led to better diagnosis and management of severe neurological conditions such as Parkinson’s disease and epilepsy. More importantly, these approaches were used to distinguish between various types of seizures based on the location and direction of the seizure foci, thereby increasing the outcomes of epilepsy surgery. A detailed study was carried out on the role of neural synchrony in brain functions with Electroencephalography (EEG). Most studies had been conducted on EEG connectivity analysis at sensor level. It is not easy to evaluate the connected networks because the volume conductive effect significantly distorts signals because of the electrical conductiveness of the head and often scalp electrodes derive input from the same sources in the brain. These factors help to estimate the real connectivity between brain regions inaccurately. The suggested approach is referred to as EEG source connectivity. The inverse problem is the estimation of the localized current dipole model from the EEG measurements. In order to solve the inverse EEG problem, advanced signal-processing algorithms such as the efficient implementation of PF have been built to facilitate direct exposure to neural dipole sources in real time and measure the connectivity of neural sources time courses using functional and effective connectivity measures.

Two new simple and effective voltage mode frequency selective structures that pass all signals are proposed and explored in this paper. The proposed structures use a single active element and three passive components in each. Dual-X second generation current conveyor (DXCCII) is employed as an active element along with two resistors and a capacitor as passive elements. The capacitor is grounded which goes well with the IC fabrication requirements. Both the structures offer low active and passive sensitivities. The presented structures also exhibit the feature of high input impedance. A comprehensive study of device non-idealities and parasitic is also included to highlight the non-ideal performance of the presented ideas. In addition, to prevent the use of passive resistors, resistor less realizations of proposed structures are also explored by replacing the passive resistors with MOS-based active resistors. A quadrature oscillator is also presented as one of the possible applications of the proposed frequency selective structures. Simulations results are in match with the theoretically analyzed performance.