Journal of Circuits, Systems and Computers

In this paper, we present second generation current-controlled conveyor (CCCII)-based simple memristor circuit which exhibits a hard-switching voltage-current relationship. The proposed memristor circuit contains only single CCCII and single grounded capacitor that are attractive for the integrated circuit designers. The proposed memristor emulator has four main advantages: hard-switching behavior, not utilizing multiplier circuit, biasing current or voltage source (excluding DC current or voltage source), and being free of body effect for all transistors. Cadence Spectre Analog Environment with TSMC 0.18$\mu$m process parameters is used for all simulations. The memristive chip occupies only 81.85$\mu$$\text{m}\times 87.76$$\mu$m area. All simulation results are presented to demonstrate the performance of the proposed circuit by changing some parameters such as frequency, temperature, DC power supply voltages and process variations. Also, the robust performance of the proposed memristor is confirmed via Monte Carlo simulations. The simulation results for designed memristor are in accordance with theoretical memristive behavior.

In the widely used single-molecule Deoxyribonucleic Acid (DNA) sequencing and patch-clamp technique, the fast capacitance (C-Fast) noise in application circuit affects the accuracy of the system measurement. In this paper, a high-performance C-Fast compensation method based on compensation circuit and fuzzy adaptive algorithm is proposed. The model of C-Fast noise is analyzed and a C-Fast compensation circuit is designed, whose parameters can be automatically calculated and adjusted by fuzzy adaptive algorithm. The method is validated through simulations and experiments on the test setup. The results indicate that the proposed method can effectively eliminate the C-Fast noise and improve the measurement accuracy.

Salt-and-pepper noise suppression for vector-valued images usually employs vector median filtering, total variation L1 model, diffusion methods and variants. These approaches, however, often introduce excessive smoothing and can result in extensive visual feature blurring and are suitable only for images with low intensity noise. In this paper, a new method, as an important preprocessing step in cyber-physical systems, is presented to suppress salt-and-pepper noise that can overcomes this limitation. This method first detects the corrupted pixels and then restores them using channel-wise anisotropic diffusion. The means is twofold. On the one hand, the marginal approach is used to perform noise suppression separately in each channel because the contaminative pixel components are of independent distribution. On the other hand, a decision-based anisotropic diffusion method is applied to each channel to restores them. The anisotropic diffusion is an energy-dissipating process with time, and dependent on geometric analysis of shape of the energy surface. Simulation results indicate that the proposed method for impulsive noise removal achieves the state-of-the-arts results.

This paper considers design procedure of fast locking time self-tuning $g_m\text{-}C$ biquadratic band-pass filter with nonlinear sliding mode control. A sliding mode controller is building block of the phase control loop (PCL) involved to push central frequency to reach input signal frequency very fast, approximately 100–200ns. The sliding mode controller is realized by using a tunable delay line, enabling optimal filter locking time for different input signal frequencies. The filter possesses low sensitivity to component discrepancy and is applied as a selective amplifier. The 0.13$\mu$m SiGe BiCMOS technology has been utilized for design and verification of the presented filter. This filter has central frequency up to 220MHz, quality factor $Q=11$ and 25dB gain.

Ultra high definition (UHD) video is considered as a technology that generates a video image with a resolution 16 times as many pixels as high definition television. Extensive and complex computational difficulties are there to generate a video in super-resolution (SR). Some extensive floating-point computations are needed for the direct implementation of area-pixel scaling, which is a factor for calculating one target pixel. In this paper, a hybrid Convolutional Neural Network and Cuckoo Search (CNN-CS) algorithm are proposed, which can replace the large scale of complex training and time-consuming machine learning technique. Cuckoo Search (CS) algorithm is based on bird’s levy-flight approach that can optimize the CNN. CS forecasting model isolates the redundant or irrelevant image patches and, therefore, it reduces the required memory space. The SR is performed effectively in hardware with less hardware utilization and memory space, where LR input data are processed line-by-line using the proposed hybrid CNN-CS algorithm. To optimize the design constraints, CS forecasting model estimates the required patches. Parallel sub pipeline (PSP) technique improves the parallelism process thereby reducing the computational complexity and improving the throughput rate and speed of execution. Finally, the proposed hybrid CNN-CS SR design is coded in Verilog HDL and is implemented with the XCKU040 FPGA device. To validate the proposed CNN-CS SR algorithm, standard datasets, such as Set-5, Set-14, BS-100 and Urban-100, are used. The visual quality of the proposed CNN-CS SR design is evaluated by the standard evaluation metrics such as peak signal-to-noise ratio (PSNR) and SSIM. The proposed hybrid CNN-CS SR design is compared with the existing state-of-the-art techniques both qualitatively and quantitatively. Experimental results demonstrate that the proposed method improved the throughput of 42.83%, memory space and power consumption are reduced to 16.16%, 63.81%, respectively, over the existing techniques.

In past years, software used to be the main concern of computer security, and the hardware was assumed to be safe. However, Hardware Trojans, which are a malicious alteration to the circuit, pose a threat to the security of a system. Trojans may be distributed across different components of the system and can bring down the security by communicating with each other. Redundancy and vendor diversity-based methods exist to detect Hardware Trojans, but with an increase in the hardware overhead. This work proposes a novel vendor allocation procedure to reduce the hardware cost that comes with Trojan detection methods. To further reduce the cost by minimizing resource requirements, an evolutionary algorithm-based Design Space Exploration methodology is proposed with options for loop unrolling and operation chaining. For reducing the cost of hardware Trojan detection and isolation, the proposed algorithm extends an existing implementation of Firefly algorithm. The proposed method is compared with the existing algorithms, using cost-based and Pareto-based evaluations. The results obtained demonstrate the ability of the new algorithm in achieving better solutions with a 77% reduction in cost when compared to the previous solutions.

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that $\mathrm{\text{switching}}+\mathrm{\text{signal}}-\mathrm{\text{broadcasting}}$ can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through $n$ switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM.

We propose the restricted-RM (RRM) wherein the bus lengths are restricted to $k=n^{\frac{1}{d}}$, $d=2,3,\dots$. We show that counting the number of 1-bits in an input of $n$ bits can be done in $2\cdot d$ steps for $d=2,3,\dots$ by an $n\times n$ RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders.

This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming.

A new algorithm for extracting common kernels and convolutions to maximally eliminate the redundant operations among the convolutions in binary- and ternary-weight convolutional neural networks is presented. Precisely, we propose (1) a new algorithm of common kernel extraction to overcome the local and limited exploration of common kernel candidates by the existing method, and subsequently apply (2) a new concept of common convolution extraction to maximally eliminate the redundancy in the convolution operations. In addition, our algorithm is able to (3) tune in minimizing the number of resulting kernels for convolutions, thereby saving the total memory access latency for kernels. Experimental results on ternary-weight VGG-16 demonstrate that our convolution optimization algorithm is very effective, reducing the total number of operations for all convolutions by $25.8\sim 26.3\%$, thereby reducing the total number of execution cycles on hardware platform by 22.4% while using $2.7\sim 3.8\%$ fewer kernels over that of the convolution utilizing the common kernels extracted by the state-of-the-art algorithm.

In this paper, we investigate discrete-time uncertain spatially interconnected systems (USISs), where uncertainties are modeled by linear fractional transformation (LFT). First, the well-posedness, quadratic stability and contractiveness of discrete-time USISs are introduced. Second, a sufficient condition is proposed to guarantee that discrete-time USISs are well-posed, quadratically stable and contractive. Then, a more tractable condition is derived to check the well-posedness, quadratic stability and contractiveness of discrete-time USISs via a modified bilinear transformation. Besides, the robust distributed filters which inherit the structure of the plants are designed. A sufficient and necessary condition is presented to guarantee the existence of the robust distributed filters. Finally, a vehicle platoon model demonstrates the effectiveness of the proposed scheme.

In the modern System on Chip (SoC)-based designs, embedded memory occupies the majority of the area. Therefore, the demand for fast self-testing plays a vital role in the SoC device as its memory density increases. The focus of this research study is to provide a self-testing mechanism integrated with the SoC design for fault diagnosis and failure analysis. In particular, this paper proposes a controller design to test memories at SoC devices, called a memory built-in self-test (MBIST) controller. This controller works on the principle of the proposed March-ee (enhanced elements) algorithm with the primary objective to improve the test speed, fault coverage, and power consumption at a low area overhead. The complete design of the MBIST controller with the associated March-ee algorithm is minimal and easy to be integrated into any SoC device to provide a vibrant feature of memory fault detection. The results obtained are compared with that provided by the existing March algorithms, using the same design specifications, where the proposed March-ee MBIST controller has shown better results in terms of power consumption, fault coverage, timing, and area.

The paper presents a two-phase interleaved boost converter (IBC) providing higher step-up conversion ratio compared to the conventional IBC. The circuit consists of a crossly connected diode-capacitor cell which provides the extra boost up. The two identical capacitors of the cell are charged in parallel and discharged in series providing high voltage gain at considerably low duty ratio. Switching operations, ripple and average currents through inductors are analyzed in continuous conduction mode (CCM). Ripple in input current is also improved. The voltage stress across the semiconductor devices is less in the proposed converter. Also, boundary load condition is derived. Small-signal modeling is carried out and a control circuit is enabled in the voltage mode control framework. Power losses are analyzed and 96.53$\%$ efficiency is achieved. Finally, the proposed converter is designed and implemented, and experimental results are provided.

In this paper, a novel partial product generation (PPG) scheme has been proposed based on the shift and the add logic of multiplier bits to introduce a radix-4 and radix-16 signed binary multiplications (SBMs). The proposed PPG methodology encodes two bits for radix-4 and four bits for radix-16 at a time, whereas the traditional modified Booth encoding (MBE) for radix-4 and radix-16 encodes three bits and five bits, respectively, at a time, which offers the reduction of the encoder combinations. In the proposed design, the multiplication sign extension is pre-decided from the most significant bit (MSB) of the multiplier and the multiplicand, thereby subtraction operation for multiplication is removed from traditional MBE. The simulation results of the proposed SBMs architecture offer a significant improvement in power, delay and power-delay-product (PDP). The PDP was reduced by $\sim 79$%, $\sim 84$% and $\sim 85$%, respectively, with proposed radix-4 SBM and by $\sim 45$%, $\sim 64$% and $\sim 72$%, respectively, with proposed radix-16 SBM for $8\times 8\text{-},16\times 16$-, and $32\times 32$-bit multiplication, respectively, when compared with the existing state-of-the-art designs.

Efficient workflow scheduling plays a critical role in achieving high performance in heterogeneous distributed computing systems. Given its key importance, workflow scheduling has been extensively studied, and various algorithms have been proposed in the literature mainly for systems with homogeneous or heterogeneous processors. Most of the algorithms leverage the average computation cost to prioritize tasks, and few focus on the combination of the level and out-degree of tasks, which both have a considerable impact on scheduling. A new list scheduling algorithm called level and out-degree earliest finish time (LOEFT) is proposed in this paper to address the problem of static workflow scheduling in a heterogeneous computing environment to reduce the workflow execution time. This algorithm has three major phases: task leveling, task prioritization and processor selection. In the task leveling phase, tasks are categorized into different groups based on depth value to ensure data transmission completeness. In the task prioritizing phase, the upward rank value is combined with the out-degree of every task to calculate the heterogeneous priority rank value on different processors and leverage the value to sort all tasks. In the processor selection phase, the selected task is assigned to the processor, which minimizes the former’s earliest finish time. The experimental simulation of randomly generated DAG and real-world application workflows proves that the LOEFT algorithm can significantly reduce the workflow execution time.

Chaotic time series prediction can be performed by applying different architectures of artificial neural networks (ANNs) that can be implemented on field-programmable gate arrays (FPGAs). However, the main challenges are the reduction of hardware resources to develop faster ANNs and the prediction capabilities for large horizons. In this manner, the contribution is devoted to introduce pipeline architectures in which some registers are placed between combinational blocks to divide the logic into shorter stages that can run with a faster clock. The cases of study are the multilayer perceptron (MLP), nonlinear autoregressive with exogenous input (NARX), and echo state network (ESN). In addition, another contribution is devoted to introduce the application of the decimation technique to extend the prediction horizon of the ANNs from 12 to 600-steps-ahead. The prediction capabilities of the MLP, NARX and ESN are compared by using eight chaotic time series with different maximum Lyapunov exponents. The pipeline FPGA-based implementations show that the ESN with a reservoir of at least 30 neurons guarantees a large prediction horizon of 600-steps-ahead. Another important advantage of the ESN is that its FPGA-based implementation can be performed by reusing one neuron, thus requiring the lowest quantity of hardware resources.

In this work, we present a technique that combines piecewise linear interpolation technique with a look-up table-based method in a novel way resulting in a logarithmic converter with higher accuracy. The piecewise linear interpolation function is obtained using a new algorithm, which aids in reducing the interpolation error. The algorithm helps in obtaining an optimized interpolation function which tracks the slope of log${}_2(1+x)$ function more accurately. As a consequence, the size of the look-up table used to correct this interpolation error reduces significantly. Further, precision of the logarithmic converter can be improved by adding additional memory without changing the overall hardware. The method of combining linear interpolation with look-up results in high accuracy with less hardware complexity compared to similar existing techniques. The proposed and existing logarithmic converter designs are synthesized on FPGA and compared for their performance. Results indicate that the proposed approach achieves an improvement of 12% to 22% in memory for accuracies ranging from 10-bit to 20-bit.

In this paper, we propose an analytic approach to the variable sifting based on weighting of qubits and gates. The proposed scheme allows us to optimally sift gates (multi-control single-target reversible gates) within a linear number of steps of computation and provides, in general, that a smaller number of SWAP gates are required to transform a reversible circuit into an Linear Nearest Neighbor (LNN) model than other competing approaches. The method is analyzed for two different models of implementations; it is verified on the experimental data and results are compared with the state-of-the-art algorithms for the design of LNN circuits.

A low complexity parallel filter architecture for image processing applications is presented. The proposed approach makes use of the transposition and custom poly-phase sub-filters design in ‘Fast FIR’ filter implementation technique to exploit the correlation among input samples by processing the intermediate signals depicting low entropy through low complexity multipliers. Despite lower complexity, the proposed approximate design performs very close to the corresponding full precision implementation as evident from the provided experimental results. The experimental evidence shows that other related efforts reported in the literature are extremely sensitive to the approximation and yields unusable results due to the propagation of error without bounds. The proposed approximate design, on the other hand, limits the inclusion of error to as low as 4% of the data samples with high Signal-to-Noise Ratio (SNR) values on average. This has been achieved through design of custom polyphase sub-filters without recursive stage and proved to be feasible irrespective of the number of kernel taps. The design efficiently maps on a Xilinx Field Programmable Gate Arrays (FPGA) and conserves chip resources by at least 6% for kernels with asymmetric fixed coefficients and 29% for symmetric ones.

Quantum cellular automata (QCA) is a promising paradigm that enables performing arithmetic and logic operations at the nanoscopic scale. The QCA utilizes the configuration of electric charges in molecular scale quantum-dots to encode binary information. Defects are very likely to occur at the nanoscale and impact the operation of QCA devices. We concentrate on a specific fault, which is caused by impurities in materials used in packaging devices. These defects may cause a single-electron to tunnel outside a QCA cell and lead to a single-electron fault (SEF). Cosmic rays may also lead to a SEF. The three-input majority gate is the primary device in the QCA paradigm. In this paper, the effect of redundant cells on the fault tolerance of the majority gate is studied in the presence of a SEF. We present figures based on the number of redundant cells, their positions, and the clock method, which are essential in designing SEF-tolerant devices.

Reversible data hiding (RDH) together with sorting is one of the key goals for reducing image distortion. This paper presents an improvement in sorting based on the double-layered RDH algorithm by modifying the dynamic variance mean (DVM) sorting models and applying an effective predictor. Seven models are investigated to achieve suitable sorting with the best prediction error (PE) for each capacity and image. The fitting weight rhombus (FWR) predictor and two-pass testing (TPT) strategy are significantly utilized to achieve small PEs and reduce distortion. The performance of the proposed RDH algorithm is compared with other similar methods using eight different images. Experiment results demonstrate that the sorting performance of the proposed method is superior to those of the previous methods.

Dual-mode patch resonator-based microstrip filters with finite real or imaginary transmission zeros are discussed by combining the analytical studies with numerical investigations. The analytical study presents the coupling scheme of a dual-mode patch resonator, while the numerical simulation discusses the coupling nature between the source (input) and load (output), which constitutes the presented half-analytical model. Furthermore, the difference of in-band losses between the two different responses can also be qualified based on this model. The contribution and novelty of this work is the coupling nature between the source and load which is explained for the first time, and based on this, the half-analytical model can further estimate the transmission zeros of the microstrip patch resonator filter. For demonstration purposes, two prototype filters that exhibit transmission zeros at the real and imaginary frequencies, respectively, are developed and confirmed experimentally. The measurements agree closely with the predications.