Journal of Circuits, Systems and Computers

Embedded distributed multimedia applications based on the use of on-chip networks for communication and messages exchange requires specific and enhanced quality of service (QoS) management. To reach the desired performances at the application level, the network-on-chip (NoC) router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process.

In this context, this paper proposes a new mechanism for QoS management in NoC. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve QoS with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.

Underwater signal classification has been an area of considerable importance due to its applications in multidimensional fields. The selection of the source specific features in a classifier is very significant, as it determines the efficiency and performance of the classifier. Discrete sine transform (DST)-based features possesses the essential traits suitable for the design of statistical models in underwater signal classifiers. These when incorporated in hidden markov models (HMMs), can provide an effective architecture which can be utilized in the classification of underwater noise sources. The design and performance analysis of a 12-state HMM-based classifier for underwater signals in Rayleigh fading channel conditions are presented in this paper. The HMMs utilizing the DST features are found to perform efficiently in underwater signal classification scenario, compared to existing cepstral feature-based classifiers. The fading channel estimation has been carried out and the classifier performance has been improved by providing Rayleigh fading compensation. The success rates of the classifier has been estimated under different operating conditions. The system performance has been analyzed in MATLAB^TM platform for the class of underwater signals, which include actual field collected data and the results have been presented in this paper.

We report a synthesis process to design the defected ground structure (DGS)-based Bessel lowpass filter (LPF). For 5-pole LPF at f_c = 2.5 GHz, its selectivity is 10.6 dB/GHz and for the DGS-based Butterworth LPF it is 12.6 dB/GHz. For the lumped elements Bessel LPF, it is only 4.84 dB/GHz. Its 20 dB rejection bandwidth is 13.1 GHz and impedance matching BW is 76%, as against 88.8% for Butterworth LPF. At f_c = 7.5 GHz, the 5-pole DGS Bessel LPF has selectivity 7 dB/GHz, 20 dB rejection BW is 13 GHz and 10 dB return loss (RL) BW in passband is 4.86 GHz (64.8%) with less than 7.9 pS group delay (GD) variation. In case of a bulky mixed microstrip-waveguide (MMW) 5-pole Bessel LPF at 7.5 GHz [W. Menzel and F. Boigelsack, 29th European Microwave Conference, Munich (1999), pp. 191–194.], reported results are: sharpness of cut-off 1.48 dB/GHz, 10 dB RL BW and GD variation are 48% and 4 pS, respectively. The improved performance the DGS-based Bessel LPF can find applications in high speed data communication, front-end of a wideband communication system and in a power amplifier, by improving the selectivity, suppression of harmonics and linear distortion.

In this paper, a new two-input three-output second-order universal filter is proposed. Two multi-output voltage controlled current followers (MO-VCCFs) and two capacitors are used in the proposed filter. The proposed filter does not have external passive resistors. It has high output impedances yielding easy cascadability. It has the property of electronic tunability. It does not need any critical passive component matching conditions. Also, it is composed of only grounded capacitors; accordingly, it is suitable for integration. Theoretical knowledge is supported via SPICE simulations.

In this paper, we optimized the performance of a 2.4 GHz variable gain low-noise amplifier for WLAN applications which provides high dynamic range with relatively low power consumption. First, the differential evolution algorithm was used to optimize the width of input transistors, then the tunable on-chip switching stage method was applied to control the amplifier gain when the input signal increases. The optimization was performed in terms of gain, noise figure (NF), IIP3 and power dissipation. The LNA has achieved a variable gain from 16.55 to 20.45 dB with excellent NF between 1.63 and 1.74 dB. Furthermore, the proposed circuit achieves a third order input intercept point of 6.6 dBm. It consumes only 10 mW from a 1.5 V supply.

A low power phase locked loop (PLL)-based modulator for wireless sensor application is presented in this paper. The modulator adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and VCO frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a structure with parallel and serial capacitances in combination with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the modulator achieves a 5.2% FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8-mW power. Loop filter and crystal are the only off-chip components.

In this paper, a variable threshold voltage metal oxide semiconductor (VTMOS) field effect transistor is used to improve an ultra-low voltage, ultra-low power current conveyor transconductance amplifier (CCTA). To achieve the desired result, an analytical subthreshold VTMOS model is used. Designs that utilize the TSMC 0.18 μm technology are verified using PSPICE simulation. The power consumption is simply 0.12 μW at a ± 0.2 V supply voltage. The proposed CCTA is synthesized using fractional-order (FO) universal filters that can simultaneously realise low pass (LP), high pass (HP) and bandpass (BP) responses with independent control of quality factor and pole frequency by transconductances (g_m). Moreover, the circuit has low input and high output impedance which would be an ideal choice for cascading in current-mode circuit. The FO filters are constructed using two FO capacitors of orders α and β (0 < α, β ≤ 1). The FO filters provide improved performance in terms of pole frequency compared with conventional-order filters. The filter has a low power consumption of 0.71 μW at a ± 0.2 V supply voltage. The validity of the proposed filter is verified through PSPICE simulations.

Reversible logic circuits consist of a chain of reversible gates with many stages. The existing transmission gate-based implementation of reversible gates severely suffers from voltage degradation because of the inherent resistive voltage drop when cascaded. In addition, the propagation delay increases quadratically with the number of transmission gates cascaded in reversible circuits. To circumvent these problems in cascaded circuits, static CMOS buffers or latches are generally inserted at intermediate stages. But the static CMOS latches are inherently irreversible and cannot be used in reversible circuits. In this work, a novel adiabatic reversible latch is proposed to regenerate the voltage levels at intermediate stages in cascaded reversible circuits. The proposed latch is placed at the target line of each transmission gate-based reversible gate implementation to restore the logic to their respective voltage levels and at the same time reduces the energy consumption significantly. In addition, the proposed adiabatic reversible gate implementations show resistance against power analysis attacks as the current drawn from the power supply matches for all cases of input stimulus.

Quality of service (QoS) and security have been considered as two competent units to govern and administer end-to-end traffic across network. A mobile ad hoc network (MANET) is a type of wireless communication, every node can act as a router or base station. Secure QoS-based routing is an important problem in MANET. A hierarchical key ranking (HKR) model is presented here for secure group communications in MANETs. To enhance the security, one-to-one random mapping is performed using hash-based message authentication code (Hash_MAC). Due to the dynamic nature and topological changes in MANET, group safeguarding is efficiently accomplished. For secure group communication and efficient QoS routing in MANET, a sector key (SK) is shared among group members to encrypt group messages which is obtained using secured message authenticated code (SMAC). The primary design is to include the group members in sector to vigorously contribute to the security of the multicast group, as a result dropping the communication and calculating load on the source. Experimental evaluation is done to estimate the performance of the proposed secure QoS routing and communication using hierarchical key ranking [SRHKR] in MANET in terms of delivery rate, security level, delay.

Semiconductor optical amplifier (SOA) is among one of the most promising candidate for all optical computation and communication technology implementation. An all optical multiplexer and demultiplexer utilizing SOA-based dual pump four-wave mixing is proposed and explained. A multiplexer and demultiplexer are very important device for both optical computation and communication system and find variety of applications. In this communication, a multiplexer and a demultiplexer are proposed using frequency encoded format. Two very simple but interesting applications of demultiplexer one as decoder of two-bit frequency encoded numbers and another as comparator of frequency encoded single-bit numbers are presented for the first time in this communication. The devices proposed here can show ultra fast speed of operation and compact with advantages of using frequency-encoding technique for representing states of information.

All optical frequency encoded logic gates NOT, OR and AND are proposed and described using polarization rotation in semiconductor optical amplifiers (SOAs). The switching power of the logic gates are very low and have capability to speed of 320 Gbps. The gates are easily integrable, simple in hardware and compatible to optical network. The input and output power requirement is included.

Hardware binding is an important step in high level synthesis (HLS). The quality of hardware binding affects the area-time efficiency of a design. The goal of a synthesis process is to produce a design which meets the area-time requirements. In this paper, we present a new hardware binding algorithm with focus on area reduction. It is called extended compatibility path-based (ECPB) hardware binding and extends the compatibility path-based (CPB) hardware binding method by exploiting inter-operation flow dependencies, non-overlapping lifetimes of variables and modifying the weight relation in order to make it application aware and thus adaptive in nature. The presented methodology also takes into account bit width of functional units (FUs) and multi mode FUs. It performs simultaneous FU and register binding. Implemented within a C to register transfer level (RTL) framework, it produces binding results which are better than those produced by weighted bipartite matching (WBM) and CPB algorithms. The use of ECPB algorithm results in an average reduction of 34% and 17.44% in area-time product over WBM and CPB methods, respectively.

This paper presents an operation of photovoltaic (PV)-based shunt active filter (SAF) for significant energy conservation, harmonic mitigation and reactive power compensation. When the PV system generates excessive or equal power required to the load demand, then the coordinating logic disconnects the service grid from the load and with a consequent reduction of panel tariff and global warming gasses. The PV module is connected to the DC side of SAF through the DC–DC converter. Converter switch is controlled by fuzzy-based perturb & observe (P&O) maximum power point tracking (MPPT) algorithm and it eliminates the drawback in the conventional PV system. The reference currents are extracted by the fuzzy logic controller-based ICos Φ control strategy. This proposed PV-SAF, if connected at the terminals of a small industry or a home or a small enlightening institution can avoid the use of interruptible power supply and individual stabilizer. An emulation using MATLAB Simulink is presented to validate the advantage of the proposed system.

This paper presents an analytical approach to design an adaptive backstepping wavelet neural network (WNN)-based controller for global asymptotic stabilization of a two-wheeled mobile robot (TWMR). It is assumed that the dynamics model is unknown, and also system exposed to an external disturbance. The design method is based on the concept of backstepping method. At the first level, adaptive backstepping controller is employed. This controller is taking advantage of WNN identifier for estimating of unknown plant dynamics. Moreover, since the adaption laws of controller are extracted in sense of Lyapunov function, the stability of closed loop is guaranteed. At the second level, robust controller is combined with primary controller, which results L₂ tracking performance and comforts lumped uncertainties exit in control system due to approximation error and external disturbance. Finally, a numerical example for the proposed control scheme is presented.

A family of current-mode universal biquad filters, realized using the concept of Sinh-Domain signal processing, is introduced in this paper. Both of them have the capability for operating in a low-voltage environment and, also, for orthogonal electronic adjustment between the resonance frequency and Q factor. Employing MOS transistors models from the AMS 0.35 μm process, the performance of the proposed topologies has been evaluated by exploiting the analog design environment of Cadence software.