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Design of EMB-Based Moore FSMs

Institute of Control & Computation Engineering, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

E-mail Address: m.kolopienczyk@issi.uz.zgora.pl

Corresponding author.

Institute of Metrology, Electronics and Computer Science, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

E-mail Address: l.titarenko@imei.uz.zgora.pl

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Alexander Barkalov

Institute of Metrology, Electronics and Computer Science, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

E-mail Address: a.barkalov@imei.uz.zgora.pl

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https://doi.org/10.1142/S0218126617501250Cited by:9 (Source: Crossref)

Abstract

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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