Narrow Results

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

D, T, SR, and JK fuzzy flip-flops are proposed and their characteristics are graphically shown in four—max-min, algebraic, bounded, drastic—logical operation systems. Some properties of there logical forms are analytically shown. The circuits of the proposed flip-flops are designed and simulated on VHDL circuit simulator. The result of synthesis shows that the areas of D, T, SR fuzzy flip-flops are nearly 0, 2/3 1/2 of that of JK fuzzy flip-flop and the delay times of D, T, SR fuzzy flip-flops are nearly 0, 2/3, 2/3 of that of JK type, respectively.