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On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects

Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, Assam, 781 039, India

E-mail Address: b.bhowmik@iitg.ernet.in

Corresponding author.

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Jatindra Kumar Deka

Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, Assam, 781 039, India

E-mail Address: jatin@iitg.ernet.in

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, and

Santosh Biswas

Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, Assam, 781 039, India

E-mail Address: santosh_biswas@iitg.ernet.in

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https://doi.org/10.1142/S0218126618502031Cited by:2 (Source: Crossref)

Abstract

Reliability has become a major concern when link-wires in on-chip networks (NoCs) suffer from stuck-at faults (SAFs). This paper presents an extended and scalable test scheme that addresses these faults in NoC links to improve yield and reliability. The scheme detects the stuck-at faults on and identifies faulty link-wires. Experiments demonstrate the effectiveness of the proposed scheme and reveal deep insights of the faults on several performance metrics.

This paper was recommended by Regional Editor Tongquan Wei.

Keywords:

References

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