Research PaperNo Access

The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs

Faculty of Information Science and Technology, Ningbo University, 818 Fenghua Road, Ningbo, Zhejiang Province, P. R. China

E-mail Address: nihaiyan@nbu.edu.cn

Search for more papers by this author

Jianping Hu

http://orcid.org/0000-0002-6469-1061

Faculty of Information Science and Technology, Ningbo University, 818 Fenghua Road, Ningbo, Zhejiang Province, P. R. China

E-mail Address: hujianping2@nbu.edu.cn

Corresponding author.

Search for more papers by this author

Xuqiang Zhang

Faculty of Information Science and Technology, Ningbo University, 818 Fenghua Road, Ningbo, Zhejiang Province, P. R. China

E-mail Address: 1603838222@qq.com

Search for more papers by this author

, and

Haotian Zhu

Faculty of Information Science and Technology, Ningbo University, 818 Fenghua Road, Ningbo, Zhejiang Province, P. R. China

E-mail Address: 1511082725@nbu.edu.cn

Search for more papers by this author

https://doi.org/10.1142/S0218126620501145Cited by:0 (Source: Crossref)

Abstract

In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the Berkeley BSIMIMG model and verified by TCAD tool. Based on these optimized devices, we designed the compact basic logic gates and two new compact D-type flip-flops. Additionally, we developed a circuit synthesis method based on Binary Decision Diagram (BDD) and the optimized compact basic logic gates. Hspice simulations show that the circuits using the proposed dual-threshold IG FinFETs have better performance than the circuits directly using the short-gate devices.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kua, E. Anderson, T.-J. King, J. Bokor and C. Hu , FinFET — A self-aligned double gate MOSFET scalable to 20nm, IEEE Trans. Electron Devices 47 (2000) 2320–2325. Crossref, Web of Science, Google Scholar
2. Z. Krivokapic et al., 14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications, 2017 IEEE Int. Electron Devices Meeting (IEDM) (San Francisco, USA, 2017), pp. 290–294. Crossref, Google Scholar
3. M. F. Zainudin, H. Hussin, A. K. Halim and J. Karim , Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration, Materials Science & Engineering Conference Series, Vol. 341 (2018), p. 012012. Crossref, Google Scholar
4. R. Sharma, R. S. Rathore and A. K. Rana , Impact of high-k spacer on device performance of nanoscale underlap fully depleted soi mosfet, Journal of Circuits, Systems, and Computers 27 (2018) 1850063. Link, Web of Science, Google Scholar
5. S. A. Tawfik and V. Kursun , FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations, Proc. 52nd IEEE Int. Midwest Symp. Circuits and Systems (Cancun, Mexico, 2009), pp. 431–434. Crossref, Google Scholar
6. D. D. Lu, A. M. Niknejad, C. Hu and C.-H. Lin , Compact modeling of variation in FinFET SRAM cells, IEEE Design Test Comput. 27 (2010) 43–50. Crossref, Google Scholar
7. J. Hu, Y. Zhang, C. Han and W. Zhang , An investigation of super-threshold FinFET logic circuits operating on medium strong inversion regions, Open Electric. Electron. Eng. J. 9 (2015) 22–32. Google Scholar
8. A. K. Dadoria, K. Khare, T. K. Gupta and R. P. Singh , New leakage reduction techniques for FinFET technology with its application, J. Circ. Syst. Comput. 27 (2018) 1850112. Link, Web of Science, Google Scholar
9. Y. Q. Wu, R. S. Wang, T. Shen, J. J. Gu and P. D. Ye , First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching, Proc. IEEE Int. Electron Devices Meeting (Baltimore, MD, USA, 2009), pp. 1–4. Crossref, Google Scholar
10. N. Seoane, G. Indalecio, E. Comesana and M. Aldegunde , Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET, IEEE Trans. Electron Devices 61 (2014) 466–472. Crossref, Web of Science, Google Scholar
11. V. Djara, V. Deshpande, M. Sousa, D. Caimi, L. Czornomaz and J. Fompeyrine , CMOS-compatible replacement metal gate InGaAs-OI FinFET with I $_{ON} = 156 μ$ A/ $μ$ m at $V_{DD} = 0.5$ V and $I_{OFF} = 100$ nA/ $μ$ m, IEEE Electron Dev. Lett. 37 (2016) 169–172. Crossref, Web of Science, Google Scholar
12. N. Seoane, G. Indalecio, D. Nagy, K. Kalna and A. J. Garcia-Loureiro , Impact of cross-sectional shape on 10-nm gate length InGaAs FinFET performance and variability, IEEE Trans. Electron Dev. 65 (2018) 456–462. Crossref, Web of Science, Google Scholar
13. H. Hahn et al., A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance, IEEE Int. Electron Devices Meeting (San Francisco, CA, USA, 2018), pp. 17.5.1–17.5.4. Google Scholar
14. M. Rostami and K. Mohanram , Dual-V_th independent-gate FinFETs for low power logic circuits, IEEE Trans. CAD Integr. Circ. Syst. 30 (2011) 337–349. Crossref, Web of Science, Google Scholar
15. S. A. Tawfik, Z. Liu and V. Kursun , Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability, Proc. Int. Conf. Microelectronics (Cairo, Egypt, 2007), pp. 29–31. Crossref, Google Scholar
16. M. Rostami and K. Mohanram , Novel dual-Vth independent-gate FinFET circuits, Proc. 2010 Asia and South Pacific Design Automation Conf. (Taipei, Taiwan, 2010), pp. 867–872. Google Scholar
17. A. Datta, A. Goel, R. T. Cakici, H. Mahmoodi, D. Lekshmanan and K. Roy , Modeling and circuit synthesis for independently controlled double gate FinFET devices, IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 26 (2007) 1959–1960. Crossref, Web of Science, Google Scholar
18. E. Giacomin, J. R. Gonzalez and P. E. Gaillardon , Low-power multiplexer designs using three-independent-gate field effect transistors, IEEE/ACM Int. Symp. Nanoscale Architectures (Newport, RI, USA, 2017), pp. 33–38. Crossref, Google Scholar
19. M. C. Wang , Independent-gate FinFET circuit design methodology, IAENG Int. J. Comput. Sci. 37 (2010) 100–105. Google Scholar
20. P. Mishra, A. Muttreja and N. K. Jha , Nanoelectronic Circuit Design (Springer, New York, 2011). Google Scholar
21. S. A. Tawfik and V. Kursun , Low-power and compact sequential circuits with independent-gate FinFETs, IEEE Trans. Electron Devices 55 (2008) 60–70. Crossref, Web of Science, Google Scholar
22. S. A. Tawfik and V. Kursun , FinFET domino logic with independent gate keepers, Microelectron. J. 40 (2009) 1531–1540. Crossref, Web of Science, Google Scholar
23. S. Chaudhuri and N. K. Jha , FinFET logic circuit optimization with different FinFET styles: Lower power possible at higher supply voltage, Proc. Int. Conf. VLSI Design and Int. Conf. Embedded Systems (Mumbai, India, 2014), pp. 467–482. Crossref, Google Scholar
24. S. A. Tawfik and V. Kursun , Multi-threshold voltage FinFET sequential circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19 (2011) 151–156. Crossref, Web of Science, Google Scholar
25. M.-H. Chiang et al., High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices, IEEE Trans. Electron Devices 53 (2006) 2370–2377. Crossref, Web of Science, Google Scholar
26. J. Westlinder, G. Sjöblom and J. Olsson , Variable work function in MOS capacitors utilizing nitrogen-controlled TiN_x gate electrodes, Microelectron. Eng. 75 (2004) 389–396. Crossref, Web of Science, Google Scholar
27. N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad and C. C. Hu , BSIM — SPICE models enable FinFET and UTB IC, IEEE Access 1 (2013) 201–215. Crossref, Web of Science, Google Scholar
28. B. Soni, G. Aryan, R. Solanky, A. Patel and R. Thakker , Performance Evaluation of 14-nm FinFET-Based Ring Counter Using BSIM-CMG Model (Springer, Berlin, 2018). Crossref, Google Scholar
29. V. P. Trivedi, J. G. Fossum, L. Mathew, M. M. Chowdhury, W. Zhang, G. O. Workman and B.-Y. Nguyen , Physics-based compact modeling for nonclassical CMOS, Proc. IEEE/ACM Int. Conf. Computer-Aided Design (San Jose, CA, USA, 2005), pp. 211–216. Crossref, Google Scholar
30. BSIM-IMG Selected as FD-SOI Standard Model, http://bsim.berkeley.edu/bsim-img-as-fdsoi-model/ (2015). Google Scholar
31. Y.-K. Lin et al., New mobility model for accurate modeling of transconductance in FDSOI MOSFETs, IEEE Trans. Electron Devices 65 (2018) 1–7. Crossref, Web of Science, Google Scholar
32. X. Zhang, J. Hu and X. Luo , Optimization of dual-threshold independent-gate FinFETs for compact low power logic circuits, Proc. 16th Int. Conf. Nanotechnology, Sendai, Japan, 2016, pp. 525–548. Crossref, Google Scholar
33. V. N. Possani et al., Exploring independent gates in FinFET-based transistor network generation, Proc. 27th Sympo. Integrated Circuits and Systems Design (Aracaju, Brazil, 2014), p. 41. Crossref, Google Scholar
34. J. P. Colinge , FinFETs and Other Multi-Gate Transistors (Springer, USA, 2008). Crossref, Google Scholar
35. T. Poiroux et al., Multiple gate devices: Advantages and challenges, Microelectron. Eng. 80 (2005) 378–385. Crossref, Web of Science, Google Scholar
36. W. Xiong et al., MuGFET CMOS Process with Midgap Gate Material, Nanoscaled Semiconductor-on-Insulator Structures and Devices (Springer, Netherlands, 2007), pp. 159–164. Crossref, Google Scholar
37. Y. Tsividis , Operation and Modeling of the MOS Transistor, 3rd edn. (Oxford University Press, 2011), pp. 25–39. Google Scholar
38. R. S. Muller and T. I. Kamins , Device Electronics for Integrated Circuits, 3rd edn. (John Wiley & Sons, USA, 2003). Google Scholar
39. Y. Liu, S. Kijima, E. Sugimata, M. Masahara, K. Endo, T. Matsukawa, K. Ishii, K. Sakamoto, T. Sekigawa, H. Yamauchi, Y. Takanashi and E. Suzuki , Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication, IEEE Trans. Nanotechnology 5 (2006) 723–730. Crossref, Web of Science, Google Scholar
40. L. Bolotov, K. Fukuda, T. Tada, T. Matsukawa and M. Masahara , Spatial variation of the work function in nano-crystalline TiN films measured by dual-mode scanning tunneling microscopy, Jpn. J. Appl. Phys. 54 (2015) 8528–8533. Crossref, Web of Science, Google Scholar
41. M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike and E. Suzuki , Demonstration, analysis, and device design considerations for independent IG MOSFETs, IEEE Trans. Electron Devices 25 (2005) 2046–2053. Crossref, Web of Science, Google Scholar
42. Synopsys, Synopsys Sentaurus Design Suite (Mountain View, CA, 2012). Google Scholar
43. H. Ni et al., Comprehensive optimization of dual threshold independent-gate FinFET and SRAM cells, Active Passive Electron. Compon. Hindawi 2018 (2018) 1–10, https://doi.org/https://doi.org/10.1155/2018/4512924. Crossref, Web of Science, Google Scholar
44. G. Paasch and H. Ubensee , A modified local density approximation. Electron density in inversion layers, Phys. Status Solidi B-Basic Solid State Phys. 113 (1982) 165–178. Crossref, Web of Science, Google Scholar
45. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F. Bauer, C. R. Cleavelin, A. M. Niknejad and C. Hu , Design of FinFET SRAM cells using a statistical compact model, Proc. Int. Conf. Simulation Semiconductor Devices Processes (San Diego, CA, USA, 2009), pp. 1–4. Crossref, Google Scholar
46. C. R. Manoj, M. Nagpal, D. Varghese and V. R. Rao , Device design and optimization considerations for bulk FinFETs, IEEE Trans. Electron Devices 55 (2008) 609–615. Crossref, Web of Science, Google Scholar
47. Y. Suzuki, K. Odagawa and T. Abe , Clocked CMOS calculator circuitry, IEEE J. Solid-State Circ. 8 (1973) 462–469. Crossref, Web of Science, Google Scholar
48. R. Brayton and A. Mishchenko , ABC: An academic industrial-strength verification tool, Proc. Int. Conf. Aided Verification, CAV 2010, Edinburgh, UK, July, 2010, pp. 24–40. Google Scholar