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  • articleNo Access

    SPTPL: A NEW PULSED LATCH TYPE FLIP-FLOP IN HIGH-PERFORMANCE SYSTEM-ON-A-CHIP (SoC)

  • articleNo Access

    AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP

  • articleNo Access

    NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

  • articleNo Access

    LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

  • articleNo Access

    DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS

  • articleNo Access

    Memory Designing Using Quantum-Dot Cellular Automata: Systematic Literature Review, Classification and Current Trends

  • articleNo Access

    Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

  • articleNo Access

    A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

  • articleNo Access

    The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs

  • articleNo Access

    Efficient Designs of Reversible Shift Register Circuits with Low Quantum Cost

  • articleNo Access

    Reliable Synchronous and Asynchronous Counter Design in QCA

  • articleNo Access

    DESIGN OF 3-VALUED R-S & D FLIP-FLOPS BASED ON SIMPLE TERNARY GATES

  • articleNo Access

    MANY-VALUED R-S MEMORY CIRCUITS

  • articleNo Access

    Towards Nonvolatile Spintronic Quaternary Flip-Flop and Register Design

    SPIN19 Jun 2023