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Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit

Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Kumaracoil, Thuckalay, Tamil Nadu 629180, India

E-mail Address: raksarian@gmail.com

Corresponding author.

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K. S. Vijula Grace

Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Kumaracoil, Thuckalay, Tamil Nadu 629180, India

E-mail Address: vijulasundar@gmail.com

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https://doi.org/10.1142/S0218126622500165Cited by:2 (Source: Crossref)

Abstract

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

This paper was recommended by Regional Editor Emre Salman.

Keywords:

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