Journal of Circuits, Systems and Computers

This paper presents an inductor less wideband low noise amplifier (LNA) with an area of 0.3mm², using 130nm SiGe BiCMOS technology targeted for 5G WiGig wireless application. A $g_m$ boosting amplifier used at the intermediate node of the cascode topology to reduce the noise contribution of the common base (CB) transistor for the first time in SiGe HBT technology. Mathematical analysis shows that the proposed high frequency $g_m$ boosting technique on the CB transistor can be optimally tuned for either low NF or high linearity. Furthermore, the circuit incorporates variable capacitors for multimode capability, ensuring optimal performance in all four WiGig channels. Post layout EM simulation of the circuit shows that the resultant LNA has a maximum gain of 21.08dB with the $-$3 dB frequency over 56GHz to 67.3GHz. The proposed LNA exhibits a minimum noise figure of 4.3dB and shows high linearity with an input referred $IP3$ of $-$2.7dB. The designed when operated using supply voltage of 1.2V consumes a total dc power of 8.9mW.

In 2017, the Government of India launched the goods and services tax (GST), referred to as “one tax, one nation, one market”. This tax all Indian businesses are subject to this tax. GST was framed with the objective of bringing tax handling for all businesses onto a single platform and developing a transparent and effective system in which all businesses will pay taxes. This paper identifies and addresses GST implementation challenges and proposes a solution, GSTChain, using blockchain network technology. Currently, GST is collected at the sellers end and bifurcated between the Indian state and central governments. GSTChain is a blockchain system based on trust and autonomy with the objective of making taxpayers’ lives easy and tax collection efficient and transparent for the government.

This paper proposes a control scheme that enhances both the power quality and voltage synchronization of the Self-Excited Induction Generator (SEIG) driven by a wind turbine supplying power to a remote region. A reactive power constraint of SEIG under load disturbances is balanced by a modified Second-Order Generalized Integrator (SOGI) with Fuzzy Logical Controller (FLC) controlled Quasi-Impedance (QZ) source network-based Static Compensator (STATCOM). The combination of STATCOM and the photovoltaic system, battery and flywheel enhances the active power potential of conventional STATCOMs by means of a hybridized STATCOM system. This system is intended for the optimum use of energy generated from renewable energy sources by physical energy storage systems such as flywheels and batteries. This tends to compensate for the deviation of both active and reactive power and hence increase in active power, reliability and system stability. For analyzing device behavior, the dynamic hybrid STATCOM model with FLC dependent ESOGI has been developed. In standalone operation, simulated and experimental findings indicate the increased capability and system efficiency under variable load conditions.

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator’s propagation delay and decreases its delay variation to 450ps. Using TSMC CMOS 130nm technology with a sampling frequency of 5.88MHz, the simulation result illustrates 788$\mu$W power consumption with the master clock frequency of 100MHz while an integral nonlinearity (INL) of $-$1.41–+0.76LSB and a differential nonlinearity (DNL) of $-$1.05–+0.05LSB is achieved in 625ps resolution. Finally, figure-of-merit (FoM) depicts 31.2fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications.

A novel optimal method of a Dynamic Voltage Restorer (DVR) supported by solid oxide fuel cell (SOFC) and its simplified topological structure are proposed. DVR is a power-electronic converter-based device, and the objective of the DVR control system is to minimize supply voltage variations at the load terminals. This is attained by generating a compensating voltage at the series injection transformer. Conventional controllers are mathematical model-based; also, the particular system varies widely, and nonlinear factors make the PI controller tuning more challenging to some extent. As a result, an intelligent PI optimization control method is essential. This paper proposes Hybrid PSOGSA to search for optimal values of two PI control parameters for the $d$–$q$-axis components by considering a novel bi-objective function. The performance of the test system is analyzed for five test scenarios using the proposed PI controller with SPSO-optimized and Ziegler–Nichols tuning methods. DVR system provides an excellent control performance in the transient and steady states for compensating the sensitive load voltages with almost zero steady-state errors. Simulation results show that the proposed approach can provide improved performance than PSO-optimized and classical PI controllers for the power quality indices measured.

Neural network technology has achieved good results in many tasks, such as image classification. However, for some input examples of neural networks, after the addition of designed and imperceptible perturbations to the examples, these adversarial examples can change the output results of the original examples. For image classification problems, we derive low-dimensional attack perturbation solutions on multidimensional linear classifiers and extend them to multidimensional nonlinear neural networks. Based on this, a new adversarial example generation algorithm is designed to modify a specified number of pixels. The algorithm adopts a greedy iterative strategy, and gradually iteratively determines the importance and attack range of pixel points. Finally, experiments demonstrate that the algorithm-generated adversarial example is of good quality, and the effects of key parameters in the algorithm are also analyzed.

The Flying Ad hoc Network (FANET) is a special type of mobile ad hoc network (MANET) that provides communications among Unmanned Aerial Vehicles (UAVs). These UAVs can reduce human intervention to a great extent by giving numerous applications under different domains such as transportation, military, healthcare, traffic monitoring, surveillance, etc. In FANET, communication is relatively challenging due to its complex infrastructure, unspecified architecture and rapid mobility of nodes. The work embodied in this paper is focused on traffic surveillance of highways using UAVs. UAVs can help to reduce the number of accidents by sharing real-time as well as the accurate status of highways among vehicles and the control station. On the other hand, they can also be used to track specific vehicles on the road. In FANET, both routing protocols and mobility models play a crucial role in the process of information exchange. In this paper, the comparison and performance evaluation of two well-known reactive routing protocols viz. Ad hoc On-demand Distance Vector (AODV) and Dynamic Source Routing (DSR) have been carried out using highway mobility model for traffic surveillance in FANET environment. Implementation of both protocols has been tested on several traffic patterns, mobility and varying network loads. Both AODV and DSR enable significant performance variations; however, they share on-demand behavior. Packet delivery fraction, average end-to-end delay, normalized routing load, packet loss, routing overhead and throughput are used to analyze the performance of both protocols. Based on experimental analysis using NS-2 under constant bit rate (CBR) and TCP traffic sources, it can be stated that AODV outperforms DSR in almost every aspect.

In this paper, a secure and low energy dynamic slicing algorithm, namely, Improved D-SMART (IM-D-SMART) based on the Data Aggregation Protocol on Slice Mix Aggregate (D-SMART) is proposed to improve the security and confidentiality of wireless sensor networks and reduce the energy consumption of nodes in data collection and transmission in wireless sensor networks. According to the importance of data, the residual energy of nodes and the relative density of nodes, the data are dynamically partitioned to improve the D-SMART algorithm. Simultaneously, sending negative number splicing is used to compensate for the loss caused by the collision of data transmission between nodes. The simulation results show that IM-D-SMART outperforms D-SMART in terms of computation, privacy and communication cost.

Centralized Personal Health Records (PHR) are mutable with compromised security as it may lead to a single point of failure. Confidentiality, protection and security are the common issues in clinical record frameworks. Specific security and protection schemes are being used to secure clinical records. Accordingly, using the Interplanetary File System (IPFS), a decentralized PHR can be maintained to allow patients to access their records without delay. Moreover, a Kademlia-based distributed hash table provides fault tolerance and enables patients to keep track of their medical history. However, a significant issue in IPFS is data availability. It is only available on the web until users or hosts of the network request each peer, later it leads to a permanent loss of data. We propose an architecture that aims to provide faster retrieval and constant PHR availability using Blockchain and IPFS. The results show that an optimal node is selected in each iteration amongst all the available adjacent nodes.

This paper presents a stochastic heuristic approach to solve numerically nonlinear differential equation (NLDE) governing the thin film flow of a third-grade fluid (TFF-TGF) on a moving belt. Moreover, the impact on velocity profile due to fluid attribute is also investigated. The estimate solution of the given NLDE is achieved by using the linear combination of Bernstein polynomials with unknown constants. A fitness function is deduced to convert the given NLDE along with its boundary conditions into an optimization problem. Genetic algorithm (GA) is employed to optimize the values of unknown constants. The proposed approach provided results in good agreement with numerical values taken by Runge–Kutta and more accurate than two popular classical methods including Adomian Decomposition Method (ADM) and Optimal Homotopy Asymptotic Method (OHAM). The error is minimized 10${}^{-1}$ times to 10${}^{-2}$ times.

The emergence of cloud computing in big data era has exerted a substantial impact on our daily lives. The conventional reliability-aware workflow scheduling (RWS) is capable of improving or maintaining system reliability by fault tolerance techniques such as replication and checkpointing based recovery. However, the fault tolerant techniques used in RWS would inevitably result in higher system energy consumption, longer execution time, and worse thermal profiles that would in turn lead to a decreased hardware lifespan. To mitigate the lifetime-energy-makespan issues of RWS in cloud computing systems for big data, we propose a novel methodology that decomposes the complicated studied problem. In this methodology, we provide three procedures to solve the energy consumption, execution makespan, and hardware lifespan issues in cloud systems executing real-time workflow applications. We implement numerous simulation experiments to validate the proposed methodology for RWS. Simulation results clearly show that the proposed RWS strategies outperform comparative approaches in reducing energy consumption, shortening execution makespan, and prolonging system lifespan while maintaining high reliability. The improvements on energy saving, reduction on makespan, and increase in lifespan can be up to 23.8%, 18.6%, and 69.2%, respectively. Results also show the potentiality of the proposed method to develop a distributed analysis system for big data that serves satellite signal processing, earthquake early warning, and so on.

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18-$\mu$m CMOS technology. In this architecture, the achieved output range is 1.5–4.8V for an input range of 1.5–3.15V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15V. In a conventional RDAC for the output voltage of 4.8V, it requires 2${}^{14}$ switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and $-$0.06 LSB, respectively, with an LSB voltage of 3mV. The one-channel area is 0.586mm $\times$ 0.017mm and the settling time is 4.25$\mu$s for 30k$\mathrm{\Omega }$ and 30pF driving load.

A highly secure communication method is essential for end users for the exchange of information which is not interpreted by an intruder. Cryptography plays a crucial role in the current and upcoming digital worlds, for secure data transmission in wired and wireless networks. Asymmetric and symmetric cryptographic algorithms encrypt data against vulnerable attacks and transfer to authenticated users. Steganography is a method for providing secure information with the help of a carrier file (text, video, audio, image, etc.). This paper proposes Deoxyribonucleic Acid (DNA)-based asymmetric algorithm which is used to encrypt the patient’s secret information and its performance is compared with ElGamal, RSA and Diffie–Hellman (DH) cryptographic algorithms. The proposed asymmetric algorithm is applied to image steganography which is used for encrypting and concealing the patient’s secret information in a cover image. The proposed method consumes less hardware resources with improved latency. Dynamic Partial Reconfiguration (DPR) allows to transform a selective area rather than complete shutdown of the entire system during bitstream configuration. Cryptosystem with DPR is designed, synthesized in Xilinx Vivado and simulated in Vivado simulator. The design is targeted at Basys3, Nexys4 DDR and Zync-7000 all-programmable SOC (AP SoC) architectures and programmed with secure partial bit files to avoid vulnerable attacks in the channel.

As the number of streaming multiprocessors (SMs) in GPUs increases, in order to gain better performance, the reply network faces heavy traffic. This causes congestion on Network-on-Chip (NoC) routers and memory controller’s (MC) buffers. By taking advantage of cooperative thread arrays (CTAs) that are scheduled locally in clusters, there is a high probability of finding the same copy of data in other SM’s $L_1$ cache in the same cluster. In order to make this feasible, it is necessary for the SMs to have access to local $L_1$ cache of the neighboring SMs. There is a considerable congestion in NoC due to unique traffic pattern called many-to-few-to-many. Thanks to the reduced number of requests that is attained by our proposed Intra-Cluster Locality-Aware (ICLA) unit, this congested replying network traffic becomes many-to-many traffic pattern and the replied data goes through the less-utilized core-to-core communication that mitigates the NoC traffic. The proposed architecture in this paper has been evaluated using 15 different workloads from CUDA SDK, Rodinia, and ISPASS2009 benchmarks. The proposed ICLA unit has been modeled and simulated in the GPGPU-Sim. The results show about 23.79% (up to 49.82%) reduction in average network latency, 15.49% (up to 36.82%) reduction in average $L_2$ cache access, and 18.18% (up to 58.1%) average improvement in the instruction per cycle (IPC).

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Fog Computing extends storage and computation resources closer to end-devices. In several cases, the Internet of Things (IoT) applications that are time-sensitive require low response time. Thus, reducing the latency in IoT networks is one of the essential tasks. To this end, fog computing is developed with a motive for the data production and consumption to always be within proximity; therefore, the fog nodes must be placed at the edge of the network, which is near the end devices, such that the latency is minimized. The optimal location selection for fog node placement within a network out of a very large number of possibilities, such as minimize latency, is a challenging problem. So, it is a combinatorial optimization problem. Hard combinatorial optimization problems (NP-hard) involve huge discrete search spaces. The fog node placement problem is an NP-hard problem. NP-hard problems are often addressed by using heuristic methods and approximation algorithms. Combinatorial optimization problems can be viewed as searching for the best element of some set of discrete items; therefore in principle, any metaheuristic can be used to solve them. To resolve this, meta-heuristic-based methods is proposed. We apply the Simulated Annealing (SA), Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) technique to design fog node placement algorithms. Genetic Algorithm is observed to give better solutions. Since Genetic Algorithm may get stuck in local optima, Hybrid Genetic Algorithm, and Simulated Annealing (GA-SA), Hybrid Genetic Algorithm and Particle Swarm Optimization (GA-PSO) were compared with GA. By extensive simulations, it is observed that hybrid GA-SA-based for node placement algorithm outperforms other baseline algorithms in terms of response time for the IoT applications.

Since the emergence of mobile devices, the architecture of mobile applications has been transformed significantly. In mobile applications, the User Interface (UI) is one of the major elements, but its development is complex and time-consuming. Existing practices do not support various presentation issues of the UI at a higher abstraction level, in a retargetable fashion, with complete tool support. Therefore, it is critical to develop a simple and automated framework for the development of mobile UIs by exploiting model-driven engineering concepts. In this paper, a Unified Modeling language (UML) profile for Mobile User Interfaces (UMMUI) has been proposed, which employs some standard UML notations for representing the mobile UI requirements at a higher abstraction level. Subsequently, a complete open-source transformation engine has been developed to automatically transform the high-level source models (in UMMUI) into the target low-level React Native implementation. Finally, the applicability of the proposed framework is validated through two benchmark case studies, i.e., Patient Management System and Library Application. The results verify that the proposed framework allows the modeling of UIs with simplicity and generates the target code automatically with minimum transformation losses.

This novel converter proposes a Multiple Input and Multiple Output (MIMO) power conversion approach for step-up and step-down processes in AC-DC, DC-DC, AC-AC and DC-AC conversions. This versatile converter is designed by using power electronic switches, for AC-DC and AC-AC conversions thyristors are preferred, whereas DC-DC and DC-AC operations require both turn-on and turn-off control so that transistor (IGBT) is the most suitable switch. The proposed converter is highly recommended for multiple source and multiple output operations, but it can perform one conversion at a time. Power rating of the converter can be up to kilowatts during DC-DC and DC-AC conversions process and AC-AC and AC-DC conversions rating may extend up to megawatts. Simulation model of the MIMO converter is examined in the MATLAB simulink model and the same verified in the real-time test bench model. Conversion in all the stages can be controlled by a digital controller according to the requirement. All four conversions can perform step-up as well as step-down process, so design of inductor and capacitor values are very much important. All four modes of operations for thyristor-based transistors and two diode-based transistors are used to ensure switching operations. Novelty of the research work is conversion of power in all the modes can be bidirectional and also in single-stage process, but in the existing systems of power conversions is a unidirectional process. Proposed single-stage power conversion has more efficiency because of low switching losses. This proposed converter was designed by using mathematical analysis, tested at simulation level and verified in the real-time experiment.

Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27Gbits/s with a total area utilization of 35digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers.