Journal of Circuits, Systems and Computers

Road side units (RSUs) can act as fog nodes to perform data aggregation at the edge of network, which can reduce communication overhead and improve the utilization of network resources. However, because the RSU is public infrastructure, this feature may bring data security and privacy risks in data aggregation. In this paper, we propose a secure multi-subinterval data aggregation scheme, named SMDA, with interval privacy preservation for vehicle sensing systems. Specifically, our scheme combines the $1\text{-}\text{R}$ encoding theory and proxy re-encryption to protect interval privacy, this can ensure that the interval information is only known by the data center, and the RSU can classify the encrypted data without knowing the plaintext of the data and interval information. Meanwhile, our scheme employs the Paillier homomorphic encryption to accomplish data aggregation at the RSU, and the Identity-based batch authentication technology to solve authentication and data integrity. Finally, the security analysis and performance evaluations illustrate the safety and efficiency of our scheme.

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.

Convolution is an important operation in neural networks which, in recent years, received significant attention from the researchers thanks to its ability to handle complex tasks such as image processing, computer vision in an efficient manner. In general, the convolution operation in neural networks considers two matrices as inputs: an image matrix representing an image and a kernel matrix required for necessary image processing operation and performs several multiplications and addition operations among the elements of image and kernel matrices. Realizing a circuit structure for matrix–matrix convolution is straightforward as each multiplication is realized by a multiplier, whereas an addition is carried out by an adder. However, the corresponding circuits result in large area, high power consumption and long delay because of the large number of multiplications and additions that are involved in the matrix–matrix convolution operations.

While, the existing approaches focus on the accelerations of this computationally intensive tasks, they often do not guarantee minimality of area, power and delay. But we show that there exists design aspects through which the circuit structures for convolution operations can be realized with less area, power and delay. To do this, we consider the kernel definitions during the design of the circuit structures since the kernel matrices are often (pre)-determined based on the desired applications. Motivated by this, we first explore the design space of the convolution operation by introducing an alternative design scheme for realizing the respective operation between two matrices keeping the image processing/neural network applications in mind. Experimental evaluations confirm the potential benefits of the proposed design scheme and demonstrate that the reductions in the area and power by approximately $88\%$ and critical path delay by approximately $31\%$ can be achieved using the proposed design scheme. In addition, the FPGA implementations of the proposed scheme also show that the reductions of approximately $93\%$ and $54\%$ in the number of LUTs and in the number of pins, respectively, can be achieved. Compared to prior works, the proposed scheme allows higher parallelism with minimum LUT utilization.

In this study, a second-generation positive current conveyor (CCII+)-based analog circuit is proposed for the electronic implementation of a different dynamical system which is an adaptation of the chaotic Lorenz differential equation set. The proposed circuit is more cost-effective and contains less active and passive elements than the circuit obtained by applying the classical parallel synthesis method with opamps. Mathematical analyses and SPICE simulations are performed for chaotic phase portraits and bifurcation diagrams. The proposed dynamical circuit is implemented on the board by using commercially available active and passive elements on the market and an experimental study is conducted. In order to demonstrate the usability of this proposed circuit in secure communication studies, three different synchronization methods are applied and one of them is implemented. The obtained experimental results are in good agreement with the mathematical analysis and simulation results.

In this work, a broadband high gain frequency selective surface (FSS)-based microstrip patch antenna is proposed. The dimensions of the microstrip antenna and proposed FSS are $22\mathrm{\text{mm}}\times 22\mathrm{\text{mm}}\times 1.6\mathrm{\text{mm}}$ and $60.8\mathrm{\text{mm}}\times 48.6\mathrm{\text{mm}}\times 1.6\mathrm{\text{mm}}$. A broadband high gain reference antenna has been selected to improve antenna performance. The reference antenna offers 1.2GHz bandwidth with 6.03dBi peak gain. Some modifications have been done on the patch and ground plane to enhance the bandwidth and gain. The impedance bandwidth of 7.70GHz (3.42–11.12GHz) with 4.9 dBi peak gain is achieved by the microstrip antenna without FSS. The antenna performance is improved by using FSS beneath the antenna structure. The maximum impedance bandwidth of 7.70GHz (3.32–11.02GHz) and peak gain of 8.6dBi are achieved by the proposed antenna with FSS. Maximum co- and cross-polarization differences are 21dB. The simulation and measurement have been done using Ansoft Designer software and vector network analyzer. The measured results are in good parity with the simulated one.

Swarm intelligent algorithms can effectively tackle optimization problems that are difficult to solve by using traditional optimization algorithms. However, with the huge increase in the time and space cost for solving optimization problems, the use of swarm intelligent algorithms suffer from the limitation of overly long computation time. Based on Spark, which is the most popular open-source distributed computing framework, this paper studies specifically using swarm intelligent algorithms to solve combinatorial optimization problems. Based on the characteristics of typical swarm intelligent algorithms, we develop Spark-based parallel implementation of these algorithms to accelerate the population updating and parameter tuning procedures involved in swarm intelligence. Specifically, we first initialize the swarm and generate the initial solution, then perform the distributed iterative evolution procedure, and finally obtain the optimal solution. In addition, in order to improve solution quality, we rely on the Spark platform to perform distributed parameter tuning. The tuning strategy first generates different parameter combinations according to a given parameter list, then execute swarm intelligent algorithms with different parameter combinations in a distributed and parallel manner, and finally determine the optimal parameter combination by comparing the solutions of all algorithms. Experimental results on benchmark datasets show that the distributed algorithms can significantly enhance the computational efficiency without affecting the solution quality.

Translation lookaside buffer (TLB) is critical to modern multi-level memory systems’ performance. However, due to the limited size of the TLB itself, its address coverage is limited. Adopting a two-level exclusive TLB hierarchy can increase the coverage [M. Swanson, L. Stoller and J. Carter, Increasing TLB reach using superpages backed by shadow memory, 25th Annual Int. Symp. Computer Architecture (1998); H.P. Chang, T. Heo, J. Jeong and J. Huh Hybrid TLB coalescing: Improving TLB translation coverage under diverse fragmented memory allocations, ACM SIGARCH Comput. Arch. News 45 (2017) 444–456] to improve memory performance. However, after analyzing the existing two-level exclusive TLBs, we find that a large number of “dead” entries (they will have no further use) exist in the last-level TLB (LLT) for a long time, which occupy much cache space and result in low TLB hit-rate. Based on this observation, we first propose exploiting temporal and spatial locality to predict and identify dead entries in the exclusive LLT and remove them as soon as possible to leave room for more valid data to increase the TLB hit rates. Extensive experiments show that our method increases the average hit rate by 8.67%, to a maximum of 19.95%, and reduces total latency by an average of 9.82%, up to 24.41%.

In the arena of Cloud Computing, the emergence of social networks and IoT increased the number of available services on the cloud platform, making service composition and optimal selection (SCOS) in Cloud Manufacturing (CMfg), NP-hard. The existing approaches for addressing SCOS often fail to offer assistance with maximized trust and satisfied QoS preferences. Hence, this research paper presents a novel TeachIng leaRning-based Optimization aLgorithm (TIROL) for achieving the optimal solution for truST enforced clOud seRvice coMposition (STORM) to assist CMfg for improving the trust value with satisfied QoS preference(s). The performance of the proposed framework has been validated using the synthetic dataset generated from different test-cases.

Experimental results show that the proposed framework is reliable and outperforms the SOTA approaches in terms of trust value maximization.

With the rapid development of mobile Internet, there is a higher demand for the real-time, reliability and availability of information systems and to prevent the possible systemic risks of information systems, various business consistency standards and regulatory guidelines have been published, such as Recovery Time Object (RTO) and Recovery Point Object (RPO). Some of the current related researches focus on the standards, methods, management tools and technical frameworks of business consistency, while others study the data consistency algorithms in the cases of large data, cloud computing and distributed storage. However, few researchers have studied on how to monitor the data consistency and RPO of production-disaster recovery, and what architecture and technology should be applied in the monitoring. Moreover, in some information systems, due to the complex structures and distributions of data, it is difficult for traditional methods to quickly detect and accurately locate the first error data. Besides, due to the separation of production data center (PDC) and disaster recovery data center (DRDC), it is difficult to calculate the data difference and RPO between the two centers. This paper first discusses the architecture of remote distributed DRDCs. The architecture can make the disaster recovery (DR) system always online and the data always readable, and support the real-time monitoring of data availability, consistency as well as other related indicators, in this way to make DRDC out-of-the-box in disasters. Second, inspired by blockchain, this paper proposes a method to realize real-time monitoring of data consistency and RTO by building hash chains for PDC and DRDC. Third, this paper evaluates the hash chain operations from the algorithm time complexity, the data consistency, and the validity of RPO monitoring algorithms and since DR system is actually a kind of distributed system, the proposed approach can also be applied to the data consistency detection and data difference monitoring in other distributed systems.

Current location-based services (LBS) continuously generate a massive amount of geo-message streams. The cluster-based subscription matching method is an effective means to feed subscribers with related geo-messages from geo-message streaming. However, current cluster-based subscription matching methods only consider the spatial relationship and textual relationship and ignore users’ social relationship. As a result, the matching results may not completely satisfy the requirements of users. In this paper, we proposed a social-aware subscription matching method by taking spatial, textual, and social factors into consideration. Then, we used a cache strategy and a Flink-based acceleration process to reduce the extra time overhead caused by computing the social relationships. A set of extensive experiments have been conducted on a real dataset. The experimental results indicate that our method improves the recall of matching results. Besides, the Flink-based acceleration process with caching can speed up the subscription matching process by a ratio of up to 3.299 compared with the state-of-the-art.

It draws researchers’ attentions how to make use of the log data effectively without paying much for storing them. In this paper, we propose pattern-based deep learning method to extract the features from log datasets and to facilitate its further use at the reasonable expense of the storage performances. By taking the advantages of the neural network and thoughts to combine statistical features with experts’ knowledge, there are satisfactory results in the experiments on some specified datasets and on the routine systems that our group maintains. Processed on testing data sets, the model is 5%, at least, more likely to outperform its competitors in accuracy perspective. More importantly, its schema unveils a new way to mingle experts’ experiences with statistical log parser.

This paper proposes a cloud computing-based approach to efficiently process the massive data produced in intelligent machine tool diagnosis flow. By collecting and extracting the vibration, power and other useful system signals during the machining operation of machine tools, the cutting process samples and cutting gap samples of machine tools can be accurately segmented, in order to construct a set of signal samples that can effectively and completely characterize the level of tool wear. We propose a visual detection method that relies on local threshold segmentation to predict tool wear status. The machine tool image is divided into several small blocks, and each image block is segmented to obtain the segmentation threshold, which is defined as the local threshold of each block. Then, the detection method scans the whole image based on the maximum local threshold among all blocks. Considering the complicated flow of visual detection and the high volume of machine tool diagnosis data, we further propose a big data processing approach which is implemented on a cloud computing architecture. By modeling the workflow of the proposed visual detection method as a directed acyclic graph, we develop a scheduling model that aims at minimizing the execution time of massive tool diagnosis data processing with available cloud computing resources. A effective metaheuristic based on search strategy of artificial bee colony is developed to solve the formulation scheduling problem. Experimental results on a cloud-based system demonstrate that, the visual detection method enhances the accuracy of tool wear detection, and the cloud-based approach significantly reduces the execution time of tool diagnosis flow by means of distributed computing.

In this paper, a novel dual-band monopole planar antenna is presented. The antenna is operated in 28/38GHz and has a bandwidth of 0.5/0.7GHz to operate in 5G frequency bands. Additionally, it exhibits a stable omni-directional radiation pattern with high gain characteristics, which helps to improve the performance of future 5G communication devices. The radiation efficiency achieved more than 94% throughout its operating bands. The numerical analysis has been carried out using a three-dimensional (3D) full-wave electromagnetic solver (ANSYS HFSS). In order to validate the numerical analysis, the proposed antenna has been fabricated and shows a good agreement with simulated results. The antenna has been designed and fabricated on Roger RT/Duroid 5880 dielectric substrate. This paper paves a new idea to design dual-band, simple and miniaturized single-element monopole planar antennas, which would be a good candidate for future millimeter-wave 5G communication systems.

The routing in vehicular delay tolerant networks (VDTNs) does not presume an end-to-end connectivity from source to destination. One substitute is to use the real-time geographical information of vehicles to relay messages. However, if mobile destination is considered, then real-time information might not be generally available due to the sparse network density in VDTN. In this paper, a geographical routing approach based on the probability delegation replication (GR-PDR) is proposed. The functionality of GR-PDR is categorized into forwarder node selection phase and buffer management phase. The forwarder node selection utilizes the advantages of delegation replication approach to conquer the constraints of routing decisions and local maximum problem. Further, the buffer management is employed to prioritize packets to ensure delivery before the expiration of message lifetime. The proposed GR-PDR ensures that the message will be forwarded to higher quality node, resulting in a high delivery ratio. The approach utilizes the advantages of single-copy and multiple-copy forwarding approaches by avoiding redundant replication and enhancing delivery probability, respectively. The performance results show that the proposed GR-PDR outperforms in terms of packet delivery ratio, average delay and network overhead, when compared with the protocols of the same segment. Statistical analysis validates the effectiveness of the proposed protocol.

In this paper, we propose an enhanced dual path attention network (EDPAN) for image super-resolution. ResNet is good at implicitly reusing extracted features, DenseNet is good at exploring new features. Dual Path Network (DPN) combines ResNets and DenseNet to create a more accurate architecture than the straightforward one. We experimentally show that the residual network performs best when each block consists of two convolutions, and the dense network performs best when each micro-block consists of one convolution. Following these ideas, our EDPAN exploits the advantages of the residual structure and the dense structure. Besides, to deploy the computations for features more effectively, we introduce the attention mechanism into our EDPAN. Moreover, to relieve the parameters burden, we also utilize recursive learning to propose a lightweight model. In the experiments, we demonstrate the effectiveness and robustness of our proposed EDPAN on different degradation situations. The quantitative results and visualization comparison can sufficiently indicate that our EDPAN achieves favorable performance over the state-of-the-art frameworks.

Finding an effective license plate localization (LPL) method is challenging owing to different conditions during the image acquisition phase. Most existing methods do not consider various low-quality image conditions that exist in real-world situations. Low-quality image conditions mean that an image can have low resolution, plate imperfection effects, variable illumination environments or background objects similar to the license plate (LP). To improve the anti-interference ability and the speed performance of algorithm, this study aims to develop a parallel partial enhancement method based on color differences that demonstrates improved localization performance for blue–white LP images under low-quality conditions. A novel color difference model is exploited to enhance LP areas and filter non-LP areas. Blue–white color ratio and projection analysis are performed to select the exact LP area from the candidates. Moreover, this study develops a parallel version based on a multicore CPU for real-time processing for industrial applications. An image database including 395 low-quality car images captured from various scenes under different conditions is tested for the performance evaluation. The extensive experiments show the effectiveness and efficiency of the proposed approach.

The evolution of multi-level inverters (MLIs) has led to an increase in their efficiency and reliability. This paper demonstrates an FPGA-based reduced switch novel Infinite-Level Inverter. Conventional two-level Voltage Fed Inverters (VFI) suffer from reduced efficiency, greater voltage distortion and higher switching losses. Multi-level inverters (MLI) outweigh the conventional inverter in terms of improved voltage profile, reduced switching losses, increased efficiency and lower component count. This paper demonstrates an FPGA-based Reduced Switch Novel Infinite-Level Inverter that achieves infinite voltage output levels; with a reduced count of passive and active elements. The proposed inverter has a high DC-link utilization factor of 1.23, reduced blocking voltage and inverter switching losses, employing a single DC source and least number of components. It outputs a sinusoidal voltage with a minimum voltage distortion of 2.1%, which lies within the approved limits of IEEE 519-2014 standard. Comparative studies of the proposed inverter are conducted with different multi-level inverter configurations. FPGA-based control of the proposed inverter reduces execution time and enhances the control performance of the inverter. Evidently, the low cost function of the proposed inverter indicates the economic feasibility of the developed inverter for low-power, low-cost applications.

Fair power allocation to the users in a power domain nonorthogonal multiple access (PD-NOMA) networks is an essential aspect. In this paper, we have proposed a coefficient-scaling-based fair power allocation scheme, for a single cell multi-user PD-NOMA network. First, we have developed a model for two users with a fixed power allocation scheme, and proposed a modified strong user fair-power allocation scheme. Furthermore, this two-user scheme is extended for an ad-hoc multi-user PD-NOMA network and a coefficient-scaling-based approach for fair power allocation is proposed to address the outage issue. The performance of the proposed schemes is evaluated through bit-error-rate, sum-rate, outage, and fairness index. The simulation results reveal a remarkable increase in fairness performance of the proposed scheme, in comparison with a state-of-the-art method.

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of $-7.18$dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6dB, a noise figure of 3.1dB and IIP3 of $-21.7$dBm. The total current drawn by the receiver is 27.3mA at a 1.2V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is $770\ast 380\mu {\mathrm{\text{m}}}^2$ whereas the proposed filter occupies $27.7\ast 21.9\mu {\mathrm{\text{m}}}^2$.

A current-mode first-order filter configuration simultaneously providing noninverting and inverting low-pass (LP) and high-pass (HP) responses depending on passive element choice is proposed. In addition, all-pass filter (APF) responses can be easily obtained with interconnection of LP and HP output currents. The proposed filter employs only two differential voltage current conveyors, a grounded resistor and a grounded capacitor, so it is suitable for integrated circuit realization. It provides the feature of high output impedance. It does not need any passive element matching constraints. A voltage-mode oscillator based on the inverting APF is presented as a typical application. The performance of the proposed configuration is verified through many SPICE simulation and experimental test results.