Journal of Circuits, Systems and Computers

Convolutional neural networks (CNNs) have emerged as a prominent choice in artificial intelligence tasks. Recent advancements in CNN designs have greatly improved the performance and energy-efficiency of several computation-intensive applications. However, in real-time applications, greater accuracy of CNN is attained at the expense of very high computational cost and complexity. Further, the implementation of real-time CNN on embedded platforms is highly challenging due to resource and power constraints. This paper addresses the aforesaid computational complexity and presents an accelerator architecture accompanied by a novel kernel design to improve overall CNN performance. The proposed kernel design introduces a computing mechanism that reduces the data movement cost in terms of computational cycle count (latency) by parallelizing the convolution processing elements. This architecture takes advantage of the overlap of spatially adjacent data. The performance of the proposed architecture is also analyzed for multiple hyper-parameter configurations. The proposed accelerator achieves an average of $16\times$ improvement in reduction of execution time than the conventional computing architecture. To analyze the proposed architecture’s performance, we validate the architecture with AlexNet and VGG-16 CNN models. The proposed accelerator architecture achieves an average of $1.7\times$ throughput improvement over state-of-the-art accelerators.

With the rapid development of information technology, internet of things, cloud computing, digital networks and 5G have become an indispensable part of our life. Due to the development of these cutting-edge digital technologies, smart cities now have become a reality. During the development of smart cities, many different sensing devices of the cities would generate lots of data. To smoothly use the massive data, the paradigm of cloud computing will be deployed by smart cities, these data will be efficiently stored and processed by the cloud servers. However, the security of data in smart cities should be guaranteed, especially for the privacy protection of data. Aiming at securely managing cloud data in smart cities, this paper proposes a set of secure cloud data computing protocols for set operations based on the Paillier encryption system. For the rational numbers which are very common in smart cities, we design a coding technology to realize the secure homomorphic computation of them. We also verify the security and correctness of our protocols through rigorous mathematical proof, and demonstrate the efficiency of our solutions by performance analysis.

This paper deals with the realization of two first-order all-pass filter (APF) structures. First structure provides both inverting and non-inverting voltage-mode APF functions. This structure utilizes one differential difference dual-$X$ second generation current conveyor (DD-DXCCII) without $Z$ terminals, one active resistor and one capacitor only. The use of active resistor makes the proposed structure electronically tunable. Therefore, the attributes such as use of single DD-DXCCII without $Z$ terminals and electronic tunability make the proposed structure simple and attractive. Conversely, second proposed circuit structure of first-order APF enriches the quality of this paper as both inverting and non-inverting APF functions in both voltage and current forms are available simultaneously within the same circuit structure. This circuit is realized with the help of one DD-DXCCII, three active resistors and one capacitor. The second circuit structure also enjoys gain controllability feature along with electronically tunable pole frequency that proves to be very essential in many of the applications. Additionally, the proposed APF structures provide the demanding feature of cascadability along with chip fabrication support. Furthermore, the performance of proposed circuits is less affected by the non-idealities and parasitic of DD-DXCCII. PSPICE simulations are provided to validate the theoretical presumptions.

Ensemble methods fabricate a sequence of classifiers for classifying fresh instances by procuring a weighted vote of their individual predictions. Toning down the error and increasing accuracy is an avant-garde problem in ensemble classification. This paper presents a novel generic object-oriented voting and weighting adapted stacking framework for utilizing an ensemble of classifiers for prediction. This universal framework operates based on the weighted average of the probabilities of any suite of base learners and the final prediction is the aggregate of their respective votes. For illustrative purposes, three familiar heterogeneous classifiers, such as the Support Vector Machine, $k$-Nearest Neighbor and Naïve Bayes, are utilized as candidates for ensemble classification using the proposed stacked framework. Further, the ensemble classifier built upon the framework is compared with others and evaluated using various cross-validation levels and percentage splits on a range of benchmark datasets. The outcome distinguishes the framework from the competition. The proposed framework is used to predict the crime propensity of prisoners most accurately, with 99.9901% accuracy.

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, $V_{\mathrm{\text{DD}}}$ collapse and 9T UV SRAM, respectively.

In this paper, fractional-order chaotic systems in an analog-based platform are realized using field programmable analog arrays (FPAA) hardware. With the help of this work, we aim to increase the complexity of chaotic systems. Approximated transfer functions in frequency domain are obtained by analyzing different values of fractional-order integrator with the Charef approximation method. In this study, fractional-order numerical calculation of Rssler and Sprott type-H chaotic systems is carried out. MATLAB Simulink model for chaotic systems that satisfy the conditions of chaos in the boundaries of fractional order value is schematically presented. Moreover, CAM designs and analysis that facilitate the realization of fractional-order transfer functions in FPAA platforms are introduced. The analog-based FPAA experimental and numerical outcomes for fractional order chaotic systems are demonstrated. The comparison of the results obtained in the numerical analysis and simulation study with the experimental results is given. This study confirms that the unpredictability of the chaos carrier signals realized by digital-based can be increased with analog-based FPAA hardware and fractional-order structures so as to provide safer transfer of information signals.

U-Net shows a remarkable performance and makes significant progress for segmentation task in medical images. Despite the outstanding achievements, the common case of defect detection in industrial scenes is still a challenging task, due to the noisy background, unpredictable environment, varying shapes and sizes of the defects. Traditional U-Net may not be suitable for low-quality images with low illumination and corruption, which are often presented in the practical collections in real-world scenes. In this paper, we propose an attention U-Net with feature fusion module for combining multi-scale features to detect the defects in noisy images automatically. Feature fusion module contains convolution kernels of different scales to capture shallow layer features and combine them with the high-dimensional features. Meanwhile, attention gates are used to enhance the robustness of skip connection between the feature maps. The proposed method is evaluated on two datasets. The best precision rate and MIoU of defect detection are 95.6% and 92.5%. The best F-score of concrete crack detection is 95.0%. Experimental results show that the proposed approach achieves promising results in both datasets. It demonstrates that our approach consistently outperforms other U-Net-based approaches for defect detection in low-quality images. Experimental results have shown the possibility of developing a mixture system that can be deployed in many applications, such as remote sensing image analysis, earthquake disaster situation assessment, and so on.

Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400MHz to 405MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680mV supply voltage in 45nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from $-$0.422V to $+1.102$V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495MHz at 0.68V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402MHz, thus making it better suitable for the MICS band of applications. Phase noise of $-96.26$dBc/Hz at an offset of 200kHz was obtained. The proposed differential DCO consumed power was 95.26$\mu$W. The figure of merit (FoM) for this DCO is $-174.39$ (dBc/Hz). The area consumed by the DCO is 0.01872mm².

In this paper, we propose a high-precision memristive neural network with neurons implemented by complementary metal oxide semiconductor (CMOS) inverters. Regarding the process variations in the memristors and the sensitivity of the memristive crossbar structure to these fluctuations, the read operation with repetitive pulses and feedback-based write in the memristors are used to implement the neural networks trained by the ex-situ method. Moreover, accurate modeling of the neuron circuit (CMOS inverter) and decreasing the mismatch between trained weights and the limited memristances fill the gap between simulation and implementation. To employ physical constraints based on the memristor framework during the training phase, a linear function is utilized to map the trained weights to the acceptable range of memristances after the training phase. To solve the vanishing gradient problem due to the use of the tanh function as an activation function and for better learning of the network, some measures are taken. Moreover, fin field-effect transistor (FinFET) technology is used to prevent the reduction of the accuracy of the inverter-based memristive neural networks due to the process variations. Overall, our implementation improves the speed, area, power-delay product (PDP), and mean square error (MSE) of the training stage by 91.43%, 95.06%, 48.29% and 81.64%, respectively.

In the paper, an event triggering adaptive control method based on neural network (NN) is proposed for a class of uncertain nonlinear systems with external disturbances. In order to reduce the network resource utilization, a novel event-triggered condition by the Lyapunov approach is proposed. In addition, the NN controller and adaptive parameters determined by the Lyapunov stability method are updated only at triggered instants to reduce the amount of calculation. Only one NN is used as the controller in the entire system. The stability analysis results of the closed-loop system are obtained by the Lyapunov approach, which shows that all the signals in the systems with bounded disturbance are semi-globally bounded. Zeno behavior is avoided. Finally, the analytical design is confirmed by the simulation results on a two-link robotic manipulator.

Embedded applications are becoming more complex and are required to utilize computing platform resources more efficiently. Existing dynamic memory allocation (DSA) schemes cannot adaptively perform memory management according to the environment in which they are located or integrate various memory allocation strategies, making it impossible to guarantee a constant execution time. Efficient memory utilization is a crucial challenge for developers, especially in embedded OSs (operating systems). In this paper, we propose an adaptive layered segregated fit (ALSF) scheme for DSA. The ALSF scheme combines dynamic two-dimensional arrays and bitmaps, completes the allocation and freeing of memory blocks within constant execution time, and uses memory splitting technology to reduce internal fragmentation. The proposed scheme also adjusts the number of segregated lists by analyzing the system’s allocation of different memory sizes, which improves the matching accuracy of memory blocks. We conducted a comparative experimental analysis and investigation of the ALSF and two-level segregated fit (TLSF) schemes in the Zephyr OS. Experiments show that the average memory utilization of the proposed ALSF scheme reaches 94.95%. Compared with the TLSF scheme, our scheme has a 12.99% higher allocation success rate in the memory-scarce environment, and the execution speeds of the two are similar.

In this paper, a compact reconfigurable tri-band/quad-band monopole antenna is presented. To achieve the multi-band behavior, two right-angled triangles were etched in a conventional rectangular patch, and a partial ground plane is used. Moreover, the proposed multi-band antenna is printed on a low cost FR4 epoxy with compact dimensions of 0.23${\lambda }_0\times 0.23{\lambda }_0\times 0.012{\lambda }_0$, where ${\lambda }_0$ is calculated at the lowest resonance frequency. To provide frequency agility, a metal strip which acts as PIN diode was embedded in the frame of the modified patch. The tri-band/quad-band antenna performance in terms of reflection coefficient, radiation patterns, peak gain and efficiency was studied. The measured results are consistent with the simulated results for both cases. The simple structure and the compact size of the proposed antenna could make it a good candidate for multi-band wireless applications.

Eight new immittance function simulators (IFSs) with only grounded passive elements are proposed in this paper. All of the IFSs consist of only two DVCC+s and a minimum number of passive components without needing any passive element matching constraints. Each of the proposed IFSs can provide one of $\pm$L with series $\pm$R and $\pm$L with parallel $\pm$R. As an application example, a second-order mixed-mode (MM) multifunction filter is developed from the proposed +L with series +R and +L with parallel +R. Furthermore, a proportional integral derivative (PID) controller is derived from the proposed +L with series +R. Many simulation results through the SPICE program and several experimental ones are included to verify the theory.

Accurate ultra-short-term load forecasting is of great significance for real-time power generation scheduling and development of power cyber physical systems (Power CPS). However, in order to forecast the future load using the current high-dimensional, diverse and heterogeneous electric power consumption information, new challenges have been raised to the effective feature selection and the accurate load forecasting algorithms. However, very limited existing works consider the feature selection for the electric power consumption information and impacts to the thereafter load forecasting model. In view of this point, features that are critical to the load forecasting are selected using an embedded feature selection algorithm based on LightGBM to form an optimal feature set, with which a sequence to sequence (S2S) and gated recurrent unit (GRU)-based ultra-short-term load forecasting model that incorporates Bahdanau attention (BA) mechanism is presented. The S2S-GRU model is based on an encoding–decoding framework that is compatible to the input and output data series with variable lengths. By introducing the BA mechanism, loss of previous information issue of GRU can be solved. Experimental results show that first the presented feature selection algorithm can help to improve the performance of the load forecasting model. Second, the presented load forecasting model can find a compromise between the forecasting efficiency and accuracy.

Due to their structure and complexity, chaotic systems have been introduced in several domains such as electronic circuits, commerce domain, encryption and network security. In this paper, we propose a novel multidimensional chaotic system with multiple parameters and nonlinear terms. Then, a two-phase algorithm is presented for investigating the chaotic behavior using bifurcation and Lyapunov exponent (LE) theories. Finally, we illustrate the performances of our proposal by constructing three (03) chaotic maps (3-D, 4-D and 5-D) and implementing the 3-D map on Field-Programmable-Gate-Array (FPGA) boards to generate random keys for securing a client–server communication purpose. Based on the achieved results, the proposed scheme is considered an ideal candidate for numerous resource-constrained devices and internet of the things (IoT) applications.

This paper discusses how to efficiently recognize flowers based on a convolutional neural network (CNN) using multiple features. Our proposed work consists of three phases including segmentation by Otsu thresholding with particle swarm optimization algorithms, feature extraction of color, shape, texture and recognition with the LeNet-5 neural network. In the feature extraction, an improved H component with the definition of WGB value is applied to extract the color feature, and a new algorithm based on local binary pattern (LBP) is proposed to enhance the accuracy of texture extraction. Besides this, we replace ReLU with Mish as activation function in the network design, and therefore increase the accuracy by 8% accuracy according to our comparison. The Oxford-102 and Oxford-17 datasets are adopted for benchmarking. The experimental results show that the combination of color features and texture features generates the highest recognition accuracy as 92.56% on Oxford-102 and 93% on Oxford-17.

The computing power of mobile devices is too limited to execute computation tasks fast. Mobile edge computing (MEC) allows mobile devices to offload tasks to near servers to reduce the completion time of the tasks (a.k.a makespan). The input data of some critical tasks should be encrypted before the offloading. Aiming at the security critical tasks in the MEC composed of multiple servers, this paper addresses to minimize the makespan by scheduling security-critical tasks. We provide the formulation of the problem which is generally an integer programming problem, and three effective composite heuristics CH1–CH3 are proposed to solve the problem. Task permutations are considered as solutions. We construct a greedy heuristic algorithm to calculate the value of the objective. These three composite heuristics consist of two phases: solution initialization and solution improvement. In the first phase, the solutions of all the proposed algorithms are generated by a task arrangement rule called Biggest data Task First (BTF), and then in the second phase, improved by three searching methods based on different neighborhoods including a insertion neighborhood, a swap neighborhood and a hybrid neighborhood, respectively. Experimental results show that CH1–CH3 outperform the well-known RoundRobin algorithm. Particularly, BTF is demonstrated to initialize highly qualified solutions, making contributions to the high effectiveness. Meanwhile, all the improvement methods are justified to be effective and the method based on the hybrid neighborhood achieves the best effectiveness.

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

Generic polar complex exponential transform (GPCET), as continuous orthogonal moment, has the advantages of computational simplicity, numerical stability, and resistance to geometric transforms, which make it suitable for watermarking. However, errors in kernel function discretization can degrade these advantages. To maximize the GPCET utilization in robust watermarking, this paper proposes a secondary grid-division (SGD)-based moment calculation method that divides each grid corresponding to one pixel into nonoverlapping subgrids and increases the number of sampling points. Using the accurate moment calculation method, a nonsubsampled contourlet transform (NSCT)–GPCET-based watermarking scheme with resistance to image processing and geometrical attacks is proposed. In this scheme, the accurate moment calculation can reduce the numerical error and geometrical error of the traditional methods, which is verified by an image reconstruction comparison. Additionally, NSCT and accurate GPCET are utilized to achieve watermark stability. Subsequent experiments test the proposed watermarking scheme for its invisibility and robustness, and verify that the robustness of the proposed scheme outperforms that of other schemes when its level of invisibility is significantly higher.

This paper deals with the design of a true random number generator (TRNG) using the fingerprint as an entropy source and its implementation in substitution box (S-box) of Advanced Encryption Standard (AES). Considering fingerprint as a unique and random arrangement of minutiae, these minutiae points are used as the source of entropy. The proposed design utilizes fewer resources minimizing hardware redundancy and enhancing the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. The data rate, speed and latency have been obtained as 40 Mbps, 5 Mbps and 305 ns, respectively. The generated random bit stream had also been sampled and converted to a binary format in MATLAB and tested through the National Institute of Standards and Technology (NIST) 800.22 statistical suite for validation. The proposed TRNG design pass efficiency achieved is more than 95% for a sample size of 10 binary sequences.

Mobile edge computing (MEC) provides users with low-latency, high-bandwidth, and high-reliability services by migrating the computing power of the cloud computing center to the edge of the network. It is thus being considered an effective solution for the contradiction between the limited computing capabilities of Internet of Things (IoT) devices and the rapid development of delay-sensitive real-time applications. In this study, we propose and design a container union file system based on the differencing hard disk and dynamic loading strategy to address the excessively long migration time caused by the bundling transmission of the file system and container images during container-based service migration. The proposed method involves designing a mechanism based on a remote dynamic loading strategy to avoid the downloading of all container images, thereby reducing the long preparation time before which stateless migration can begin. Furthermore, in view of the excessive latency of the edge service during the stateful migration process, a strategy for avoiding the transmission of the underlying file system and container images is designed to optimize the service interruption time and service quality degradation time. Experiments show that the proposed method and strategy can effectively reduce the migration time of container-based services.