Application of an AES encryption and decryption system to an embedded processor
This work is supported by the National college students innovation training program (No. 201310681012).
This work is supported by the Applied Basic Research Programs of Yunnan Province (No. 2012FD020);
This work is supported by the Science Foundation of Education Department of Yunnan Province (No. 2012C086);
Using the advanced encryption algorithm AES [1][2], an encryption and decryption IP core is designed for embedded processors. Using the FPGA on-chip storage module and the reconfigurable S box, the key and the original data are managed with a dedicated storage method, to be locked in the kernel. In order to make the IP core able to be flexibly used in the Nios II embedded system, the corresponding interface and its address mappings are designed in accordance with the Avalon bus interface specifications. The IP core can thus be easily customized in the Nios system. The Nios II processor, customized encryption and decryption components, network controller, memory and other corresponding peripheral equipment are composed to a hardware platform by using SOPC technology. For the purpose of automation control, corresponding software is written to make it a real-time network encryption and decryption system.
