Research PaperNo Access

A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design

Mansi Jhamb

http://orcid.org/0000-0002-7975-8505

University School of Information Communication and Technology, GGSIPU, Sector-16C, Dwarka, New Delhi, India

E-mail Address: mansi.jhamb@ipu.ac.in

Corresponding author.

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Vinod Kumar Khera

Continental Devices India (P) Limited, Delhi, India

E-mail Address: vinodkhera@gmail.com

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Piyush Pant

University School of Information Communication and Technology, GGSIPU, Sector-16C, Dwarka, New Delhi, India

E-mail Address: piyushpant55@gmail.com

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, and

Hinduja Pudi

University School of Information Communication and Technology, GGSIPU, Sector-16C, Dwarka, New Delhi, India

E-mail Address: hindujaiiit@gmail.com

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https://doi.org/10.1142/S0218126619502347Cited by:0 (Source: Crossref)

Abstract

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

This paper was recommended by the Regional Editor Emre Salman.

Keywords:

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