Journal of Circuits, Systems and Computers

This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper $-$3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-$\mu$m technology, and consumes 0.022mm² and 0.27mm² of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8V, power consumption of the proposed amplifier is 36.7$\mu$W with the simulated input-referred noise of 4$\mu {\mathrm{\text{V}}}_{\mathrm{\text{rms}}}$ over 1Hz–10kHz for each channel. The amplifier also provides an output swing of 0.95 V_pp with a total harmonic distortion of $-$50dB at the frequency of 1kHz.

This work proposes a simple transformation methodology of normal nonlinear resistors/conductors to their inverted topologies in their floating and grounded versions (NNR/C). It is demonstrated that inverted topologies can also be configured as incremental or decremental nonlinear resistors/conductors. The main fingerprints of an NNR/C are holding up after the transformation and it is demonstrated that an inverse nonlinear resistor/conductor becomes a linear resistor/conductor when the operating frequency of the signal source decreases, inverse behavior in comparison with one memristor. Illustrative examples are given for floating and grounded nonlinear resistors and in both configurations. HSPICE simulation results are provided confirming the theory. Moreover, the normal and inverses resistors can be reconfigured in order to be used in future applications such as programmable analog circuits.

Due to the ultra-high carrier mobility and ultralow resistivity of Graphene channel, a Graphene field effect transistor (GFET) is an interesting candidate for future RF and microwave electronics. In this paper, the introduction and review of existing compact circuit-level model of GFETs are presented. A compact GFET model based on drift-diffusion transport theory is then implemented in Verilog-A for RF/microwave circuit analysis. Finally, the GFET model is used to design a GFET-based distributed amplifier (DA) using advanced design system (ADS) tools. The simulation results demonstrate a gain of 8dB, an input/output return loss less than $-$10dB, $-$3dB bandwidth from DC up to 5GHz and a dissipation of about 60.45mW for a 1.5V power supply. The main performance characteristics of the distributed amplifier are compared with 0.18$\mu$m CMOS technology.

In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature.

This paper presents the design of Single and Double Layer microstrip patch antennas for ultra-wideband applications. This structure consists of a square patch with a partial ground plane, fed by a 50$\mathrm{\Omega }$ microstrip line. This antenna is designed for a system to detect malignant tumors by microwave imaging. Prototypes of the two antennas are fabricated and tested with a network analyzer. The proposed antenna can achieve an ultra-wide bandwidth with VSWR$<$2 from 3.82GHz to 11.72GHz for single layer antenna and from 3.2GHz to 10.95GHz for double layer antenna, with stable and bi-directional radiation pattern. The gain is good and has a peak value of 6.5dBi. The simulation of this antenna has been performed using Ansoft High Frequency Structure Simulator (HFSS) and Computer Simulation Technology-Microwave Studio (CST).

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

In this paper, a different dual-band asymmetric Doherty power amplifier (ADPA) with a novel dual-band bandpass filter (DBBPF) with quad-section stepped impedance resonators (SIRs) is presented. This specific DBBPF rejects the annoying frequencies of the second and third harmonics in the dual-band and contributes considerably to performance improvement of ADPA. This structure is confirmed with the design, simulation, implementation and testing of a 10 W GaN-based ADPA for global system for mobile communications (GSM) and worldwide interoperability for microwave access (WiMAX) applications at 1.84 and 3.5GHz, respectively. In the measurement results, the ADPA defines a drain efficiency (DE) of 63.7% with an output power of 35dBm and power gain is 14.2dB, and a DE of 47.5% with an output power of 34.5dBm and power gain is 10.4dB at the 9dB output power back-off (OBO) from the saturated output power in the two frequency bands. Linearity effects, applying 10MHz 16 QAM signal and a 5MHz WiMAX signal, display an adjacent channel leakage ratio of $-48.9$ and $-47.3$dBc with the average output power of 36.8/36dBm at 1.84/3.5GHz, respectively.

Wireless local area networks (WLANs) are currently playing an important role in serving the indoor traffic demand. Therefore, there is a need for software-defined radio platforms (SDRs) that can enable the solutions used in these systems to be tested in real environments as well as simulated results. In this paper, we present the SDR-based wireless receiver platform for determining the real-time WLANs performance and provide the comparison of the different channel estimation methods for IEEE 802.11g based on orthogonal frequency division multiplexing (OFDM) operations. The implementation of the receiver comprises the universal software radio peripheral and National Instruments LabVIEW. To determine the real-time receiver tool performance, we emphasized necessary signal processing techniques and different channel estimation methods with varying experimental parameters in real wireless environments. Experimental results report that the SDR-based receiver tool with the LabVIEW in real-time provides the throughput of the OFDM wireless network. The captured throughput performance concerning frame error rate by the receiver is also scrutinized with different channel estimation methods.

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.

Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180nm 1.8V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.

Many literatures have discussed fractional order memristor and memcapacitor-based chaotic oscillators but the entire oscillator model is considered to be of fractional order. My interest is to propose a nonlinear oscillator with considering only the memcapacitor element of fractional order. Hence, I propose a fractional order memcapacitor (FMC)-based novel chaotic oscillator. The complete mathematical model for the proposed oscillator is derived and presented in this paper. The dimensionless state equations are then analyzed by using the equilibrium points and their stability, Eigen values, Kaplan–Yorke dimensions and Lyapunov exponents. To understand the complete dynamical behavior, bifurcation graphs are obtained and presented. Finally, the proposed fractional memcapacitor oscillator is implemented by using the shelf components.

Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ($g_{\mathrm{\text{ds}}}$), transconductance ($g_m$), gate to drain capacitance ($C_{\mathrm{\text{gd}}}$) and gate to source capacitance ($C_{\mathrm{\text{gs}}}$) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than $16\%$ NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.

This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46GHz for the tuning voltage of 0.3–1.5V. It consumes a low dc power ranging from 2.44mW to 4.79mW for the specified tuning range. The variation of phase noise ranges from $-83.03$dBc/Hz to $-78.65$dBc/Hz at 1MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of $-148.85$dBc/Hz with a differential output power of 1.8dBm at tuning voltage of 0.7V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.

This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation $sin(\beta )\approx \beta$, which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes $0.5$, $0.25$ and $0.125$, respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.

Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.

Modern GPUs can execute multiple kernels concurrently to keep the hardware resources busy and to boost the overall performance. This approach is called simultaneous multiple kernel execution (MKE). MKE is a promising approach for improving GPU hardware utilization. Although modern GPUs allow MKE, the effects of different MKE scenarios have not adequately studied by the researchers. Since cache memories have significant effects on the overall GPU performance, the effects of MKE on cache performance should be investigated properly. The present study proposes a framework, called RDMKE (short for Reuse Distance-based profiling in MKEs), to provide a method for analyzing GPU cache memory performance in MKE scenarios. The raw memory access information of a kernel is first extracted and then RDMKE enforces a proper ordering to the memory accesses so that it represents a given MKE scenario. Afterward, RDMKE employs reuse distance analysis (RDA) to generate cache-related performance metrics, including hit ratios, transaction counts, cache sets and Miss Status Holding Register reservation fails. In addition, RDMKE provides the user with the RD profiles as a useful locality metric. The simulation results of single kernel executions show a fair correlation between the generated results by RDMKE and GPU performance counters. Further, the simulation results of 28 two-kernel executions indicate that RDMKE can properly capture the nonlinear cache behaviors in MKE scenarios.

Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

In this paper, we derive the numerical solutions of the various fractional-order Riccati type differential equations using the third-kind Chebyshev wavelet operational matrix of fractional order integration (C3WOMFI) method. The operational matrix of fractional order integration method converts the fractional differential equations to a system of algebraic equations. The third-kind Chebyshev wavelet method provides sparse coefficient matrices, therefore the computational load involved for this method is not as severe and also the resulting method is faster. The numerical solutions agree with the exact solutions for non-fractional orders, and also the solutions for the fractional orders approach those of the integer orders as the fractional order coefficient $\alpha$ approaches to 1.