LEAKAGE POWER REDUCTION THROUGH DUAL Vth ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION
Abstract
With technology scaling, leakage power has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual Vth assignment, which was an effective method to reduce leakage power in the past, is also effective in today's technologies with certain modifications. In this paper, based on our statistical timing analysis (SSTA) framework, we presented a dual Vth assignment method which can effectively reduce the leakage power even in the presence of large Vth variation. Besides, taking the correlation between gates into account, we propose a novel statistical DAG pruning method to speed up the dual Vth assignment algorithm. Experimental results show that statistical dual Vth assignment can reduce on average 95% and 40% more leakage current compared with the conventional static method, without affecting the performance constraints under 180 nm and 90 nm technology nodes. Also our statistical DAG pruning method can reduce 30% gates in the circuit on average and save up to 50% of the total runtime in the 90 nm technology node.
This work was supported by grants from 863 program of China (No. 2009AA01Z130), and NSFC (No. 60870001, 90207002) and TNList Cross-discipline Foundation.