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In this paper, we propose an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined rendering engines. Based on this analysis, we propose an energy efficient memory address converter for an SoC-based 3D graphics system with an SDRAM frame buffer. About 30% of energy reduction and 20% of runtime reduction is obtained with the address converter. With dynamic power management feature of SDRAM, the energy gains increase to about 50%. The energy and runtime gains are generated by an access pattern analysis based division and assignment of frame buffer onto multiple memory modules. With this proposed access pattern analysis, a frame buffer system optimization of an IP-based 3D graphics accelerator can be performed at early architecture design level.

This study aims to contribute to the electronics education through the use of Augmented Reality (AR) technology, and thus, limit the dependency on a physical environment and the equipment required for the experiments performed in electronics education. In this regard, an Augmented Reality-based mobile application (ARElectronicLab) has been designed to provide a technology–reality blended experience of electronic circuits in real physical life. This AR-based mobile application has been used to create simulations of diode clipper circuit and inverting operational amplifier circuit. The mobile application operates with a marker in real life and enables monitoring of 3D simulations of electronic components through a touch screen. Hence, the application offers a real-like experience and brings an innovative and enriching perspective into the electronics education.