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This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

An analysis of first-order polarization-mode dispersion (PMD) effects in a 40-Gb/s optical system is used to compare different electronic equalizer architectures as potential PMD compensators. Both linear and nonlinear equalizers are considered employing symbol-spaced and fractionally-spaced taps. It is found that a decision feedback equalizer consisting of a 3-tap symbol-spaced feedforward equalizer and a 1-tap feedback equalizer effectively eliminates PMD as the dominant length-limiting factor in most 40-Gb/s optical systems. Such an equalizer would entail less complexity than several previously reported electronic PMD compensators.

To combat the performance deterioration brought by the time-varying propagation conditions and multiuser/intersymbol interference in the CDMA system, this paper proposes a novel means of adaptive equalizer based on QR Decomposition-based Recursive Least Square (QRD-RLS) algorithm to replace the conventional RAKE receiver. The RLS algorithm has been exploited due to its relatively superior convergence property in comparison with other adaptive filtering algorithms. However, the high quality brings about high computational complexity as well. With regards to such a side-effect, the CORDIC algorithm has been exploited and it plays an essential role in the hardware implementation of the new approach. The proposed RLS structure is simulated extensively under different channel parameters and performance is compared against traditional RAKE structure.

An analysis of first-order polarization-mode dispersion (PMD) effects in a 40-Gb/s optical system is used to compare different electronic equalizer architectures as potential PMD compensators. Both linear and nonlinear equalizers are considered employing symbol-spaced and fractionally-spaced taps. It is found that a decision feedback equalizer consisting of a 3-tap symbol-spaced feedforward equalizer and a 1-tap feedback equalizer effectively eliminates PMD as the dominant length-limiting factor in most 40-Gb/s optical systems. Such an equalizer would entail less complexity than several previously reported electronic PMD compensators.

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a 1-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.