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A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009$\mu {\mathrm{\text{m}}}^2$, a worst case delay of 858ps, and a power consumption of 898uW at 1G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600$\mu {\mathrm{\text{m}}}^2$) of the total comparator area and contributes 54% (484$\mu$W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and $V_{\mathrm{\text{aq}}}$ (equal to $V_{\mathrm{\text{REF}}}$/4) are combined together and optimized to realize the proposed switching scheme. $V_{\mathrm{\text{aq}}}$ is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18$\mu$m CMOS technology with a supply voltage of 0.6V and at a sampling rate of 20kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

An area-efficient and low-energy switching method for the successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. Unlike most switching methods, the proposed switching method resolves the first three bits by using asymmetric binary search algorithm. Benefiting from the novel reference voltages – $V_{\mathrm{\text{ref}}}$, $V_{\mathrm{\text{aq}}}$(1/4$V_{\mathrm{\text{ref}}}$), ground, this proposed switching method achieves 87.5% area reduction and 98.71% energy reduction over the conventional method. Furthermore, it also achieves good linearity.