[Keyword: BER] AND [All Categories: Mechanical Engineering] : Search

System Upgrade on Tue, May 28th, 2024 at 2am (EDT)

Existing users will be able to log into the site and access content. However, E-commerce and registration of new users may not be available for up to 12 hours.
For online purchase, please visit us again. Contact us at customercare@wspc.com for any enquiries.

Advanced Search

SEARCH GUIDE

Bestsellers

Classical and Computational Solid Mechanics

Classical and Computational Solid Mechanics
2^nd Edition
by Y C Fung, Pin Tong and Xiaohong Chen

Introduction to Micromechanics and Nanomechanics

Introduction to Micromechanics and Nanomechanics
2^nd Edition
by Shaofan Li and Gang Wang

Practical Railway Engineering

Practical Railway Engineering
2^nd Edition
by Clifford F Bonnett

Results: 1 - 1of1

Follow results:

per page:

Sort: Relevance

Context for search term 1Search term 1*

All Dates

LastSelect static range

Custom Range

Select starting monthSelect starting year

Select ending monthSelect ending year

Search name	Searched On	Run search
[Keyword: Hap] AND [All Categories: Orthopaedics / Biomechanics / Rheumatology] (1)	30 Mar 2025	Run
[Keyword: PCB] AND [All Categories: Surface Science] (1)	30 Mar 2025	Run
[Keyword: CFD] AND [All Categories: Engineering] (63)	30 Mar 2025	Run
[Keyword: BER] AND [All Categories: Mechanical Engineering] (1)	30 Mar 2025	Run
[Keyword: Hap] AND [All Categories: Superconductivity & Magnetic Materials] (1)	30 Mar 2025	Run

chapterNo Access
EQUALIZERS FOR HIGH-SPEED SERIAL LINKS
- PAVAN KUMAR HANUMOLU,
- GU-YEON WEI, and
- UN-KU MOON
Design of High-Speed Communication Circuits01 Jan 2006
Preview Abstract
In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

1