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During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the fields of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background effects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background effects leads to a better Trojan-to-background-effect ratio and more (by about 1.7 times) Trojan detectability.

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.

In past years, software used to be the main concern of computer security, and the hardware was assumed to be safe. However, Hardware Trojans, which are a malicious alteration to the circuit, pose a threat to the security of a system. Trojans may be distributed across different components of the system and can bring down the security by communicating with each other. Redundancy and vendor diversity-based methods exist to detect Hardware Trojans, but with an increase in the hardware overhead. This work proposes a novel vendor allocation procedure to reduce the hardware cost that comes with Trojan detection methods. To further reduce the cost by minimizing resource requirements, an evolutionary algorithm-based Design Space Exploration methodology is proposed with options for loop unrolling and operation chaining. For reducing the cost of hardware Trojan detection and isolation, the proposed algorithm extends an existing implementation of Firefly algorithm. The proposed method is compared with the existing algorithms, using cost-based and Pareto-based evaluations. The results obtained demonstrate the ability of the new algorithm in achieving better solutions with a 77% reduction in cost when compared to the previous solutions.

The design complexity and outsourcing trend of modern integrated circuits (ICs) have increased the chance for adversaries to implant hardware Trojans (HTs) in the development process. To effectively defend against this hardware-based security threat, many solutions have been reported in the literature, including dynamic and static techniques. However, there is still a lack of methods that can simultaneously detect and diagnose HT circuits with high accuracy and low time complexity. Therefore, to overcome these limitations, this paper presents an HT detection and diagnosis method for gate-level netlists (GLNs) based on different machine learning (ML) algorithms. Given a GLN, the proposed method first partitions it into several circuit cones and extracts seven HT-related features from each cone. Then, we repeat this process for the sample GLN to construct a dataset for the next step. After that, we use K-Nearest Neighbor (KNN), Decision Tree (DT) and Naive Bayes (NB) to classify all circuit cones of the target GLN. Finally, we determine whether each circuit cone is HT-implanted through the label, completing the HT detection and diagnosis for target GLN. We have applied our method to 11 GLNs from ISCAS’85 and ISCAS’89 benchmark suites. As shown in experimental results of the three ML algorithms used in our method: (1) NB costs shortest time and achieves the highest average true positive rate (ATPR) of 100%; (2) DT costs longest time but achieve the highest average true negative rate (ATNR) of 98.61%; (3) Compared to NB and DT, KNN costs a slightly longer time than NB but the ATPR and ATNR values are approximately close to DT. Moreover, it can also report the possible implantation location of a Trojan instance according to the detecting results.

Hardware Trojans (HT) are tiny, malicious circuits intentionally designed by an adversary. The existing works found in the literature on gate-level netlists are mainly based on supervised classification with few attempts at unsupervised clustering. However, the over-reliance on pre-defined structural features used in these supervised classification methods makes them vulnerable to the new Trojan attacks, whereas most unsupervised methods ignore this feature completely. This work presents an unsupervised approach for HT net detection based on the structural features required for small rare-event triggered HTs irrespective of the payload. The proposed work uses k-means clustering on these features to reduce the search space. A new metric based on combinational controllability is applied next to detect the possible trigger net. Experimental results of fifteen selected Trust-HUB benchmarks show the capability of the proposed technique against different types of HT triggers. Results show that the proposed approach reduces the search space massively (up to 99%) while running within a reasonable time frame.

Physical hardware trojan modifies registry values, leak sensitive data and result in device degradation failure. Therefore, there is great significance to develop effective hardware trojan detection methods and to study the logic circuit transmission characteristics and the chip degradation failure mechanism caused by physically injected hardware trojan. In this paper, ATLAS simulation devices were tested using hot carrier degradation (HCD) stress model to study the degradation failure process of injected hot carrier hardware trojan on a MOSFET device. Another MOSFET was combined with hot carrier injected hardware trojan MOSFET to establish an inverter logic circuit by utilizing the ATLAS device simulation system with SmartSpice simulator. The effects of physical hardware trojan and the W/L value of a hardware trojan transistor on logic circuit output characteristics were studied. The experimental results demonstrated that the negative impact of hardware trojan on logic circuit DC current output characteristic is more significant than the AC transient time characteristic. Therefore we propose a convenient and effective method to detect the injection of physical hardware trojan in packaged chips. Moreover, the test procedure is a feasible operation method to detect physical hardware trojans.