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Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated circuit. A new methodology is proposed in this paper for buffer insertion and sizing in an H-tree clock distribution network. The objective of the algorithm is to minimize the total power consumption while satisfying the maximum acceptable clock transition time constraints at the leaves of the clock distribution network for maintaining high performance. The new methodology employs nonuniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network. The proposed algorithm provides up to 30% savings in the total power consumption without sacrificing clock skew as compared to a standard algorithm with uniform buffer insertion aimed at maintaining uniform transition time constraints at all the nodes of a clock tree in a 180 nm CMOS technology.

While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube (CNT) interconnects, especially single-walled CNTs (SWCNTs) bundle interconnects, have become a promising replacement material. Nevertheless, physical design optimization techniques are still needed to allow them achieving the desired performances. While the preliminary conference version of this work [L. Liu, Y. Zhou and S. Hu, Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2014] designs the first timing driven buffer insertion technique for SWCNT interconnects, it only considers resistive and capacitive effects but not inductive effects. Although inductance could be negligible for prevailing CNT-based circuit designs, it becomes important when designing ultra-high performance chips in the future. Thus, this paper considers buffering inductive bundled SWCNTs interconnects through developing a dynamic programming algorithm for buffer insertion using the RLC tree delay model. Our experiments demonstrate that bundled SWCNTs interconnect-based buffering can effectively reduce the delay by over $3\times$ when inductive effects are considered. With the same timing constraint, bundled SWCNTs interconnect-based buffering can save over 20% buffer area compared to copper interconnect based buffering, while still running about $2\times$ faster.

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

This paper introduces a new technique for analyzing the behavior of global interconnects in FPGAs, for nanoscale technologies. Using this new enhanced modeling method, new enhanced accurate expressions for calculating the propagation delay of global interconnects in nano-FPGAs have been derived. In order to verify the proposed model, we have performed the delay simulations in 45 nm, 65 nm, 90 nm, and 130 nm technology nodes, with our modeling method and the conventional Pi-model technique. Then, the results obtained from these two methods have been compared with HSPICE simulation results. The obtained results show a better match in the propagation delay computations for global interconnects between our proposed model and HSPICE simulations, with respect to the conventional techniques such as Pi-model. According to the obtained results, the difference between our model and HSPICE simulations in the mentioned technology nodes is (0.29–22.92)%, whereas this difference is (11.13–38.29)% for another model.