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Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs’ correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs.