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A systematic approach for designing Boolean logic gates is presented in this paper. A single array of Carbon nanotube field effect transistor (CNFET) capacitors is utilized as a voltage divider of input signals. Then, a special path, which is consisted of CNFETs with different threshold voltages, connects the proper voltage source to the output node for each voltage level. The main concept is illustrated with the concentration on 3-input functions. However, some other logic gates with higher number of input variables are also proposed within the paper. The sensitivity to diameter variation of CNTs is measured by applying Monte Carlo analysis. It is not needed to use Karnaugh map to simplify expressions and the designs structured with the new method, benefit from low transistor count and a fixed critical path regardless of the number of input variables in comparison with conventional and standard circuitry design methods. Several practical circuits are also deigned, which have the capability of working in low voltages.

Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of $4.5\times$ area overhead if the fraction of metallic CNTs is reduced to 30%.

This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs.

This paper presents a new circuit structure of a multi-mode active filter, using only 16 transistors and 2 grounded capacitors in carbon nanotube field-effect transistor (CNFET) technology which is biased at $\pm 0.5$V supply. The proposed multi-input, single-output (MISO) filter has the capability of working as low-pass, band-pass, high-pass, band-stop and all-pass filters in all the operating modes (voltage, current, transconductance and transresistance). In addition, the quality factor ($Q$) parameter can be tuned electronically independent of the center frequency (${\omega }_0$). The HSPICE simulation results show that the proposed filter consumes only 971$\mu$W at 1GHz center frequency, assuming $C_1=C_2=0.1$pF and the nanotube pitch parameter of ($S=20$ nm) and the chiral vector of (22,0), while the number of nanotubes is considered as $N=16$ for all the transistors. Moreover, the main circuit performances such as the center frequency and the power consumption of the circuit vary by 5.4% and 11.6%, respectively, for the standard temperature variation.

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs’ correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs.

Electronic devices based on carbon nanotubes (CNTs) show potential for circuit miniaturization due to their superior electrical characteristics and reduced dimensionality. The CNT field effect transistors (CNFETs) offer breakthrough in miniaturization of various electronic circuits. Investigation of ballistic transport governing the operation of CNFETs is essential for understanding the device's functional behavior. This investigation is focused on a study of current–voltage characteristics of device behavior in hard saturation region. The investigation utilizes a set of current–voltage characteristics obtained on typical devices. This work is an extension of our earlier work describing application of our approach to Si-MOSFET behavior in the saturation region.

In the last 50 years, the feature size of the fabrication process for integrated circuits has continuously shrunk, corroborating Moore's Law that the feature size will be halved every 18 months. Recently, however, the problems caused by highly integrated CMOS devices such as large leakage current, high temperature when operating and high energy consumption became a huge barrier impeding the development of integrated circuits. In 1998, CNFET was proposed, and its good electrical characteristics attracted a lot of attention. CNFET is the best potential device to replace traditional CMOS devices. In this paper, a CNFET based full adder with mirror structure was thus proposed, and a comparison between CNFET full adder and conventional CMOS full adder was made.