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A systematic approach for designing Boolean logic gates is presented in this paper. A single array of Carbon nanotube field effect transistor (CNFET) capacitors is utilized as a voltage divider of input signals. Then, a special path, which is consisted of CNFETs with different threshold voltages, connects the proper voltage source to the output node for each voltage level. The main concept is illustrated with the concentration on 3-input functions. However, some other logic gates with higher number of input variables are also proposed within the paper. The sensitivity to diameter variation of CNTs is measured by applying Monte Carlo analysis. It is not needed to use Karnaugh map to simplify expressions and the designs structured with the new method, benefit from low transistor count and a fixed critical path regardless of the number of input variables in comparison with conventional and standard circuitry design methods. Several practical circuits are also deigned, which have the capability of working in low voltages.

Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of $4.5\times$ area overhead if the fraction of metallic CNTs is reduced to 30%.

This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs.

This paper presents a new circuit structure of a multi-mode active filter, using only 16 transistors and 2 grounded capacitors in carbon nanotube field-effect transistor (CNFET) technology which is biased at $\pm 0.5$V supply. The proposed multi-input, single-output (MISO) filter has the capability of working as low-pass, band-pass, high-pass, band-stop and all-pass filters in all the operating modes (voltage, current, transconductance and transresistance). In addition, the quality factor ($Q$) parameter can be tuned electronically independent of the center frequency (${\omega }_0$). The HSPICE simulation results show that the proposed filter consumes only 971$\mu$W at 1GHz center frequency, assuming $C_1=C_2=0.1$pF and the nanotube pitch parameter of ($S=20$ nm) and the chiral vector of (22,0), while the number of nanotubes is considered as $N=16$ for all the transistors. Moreover, the main circuit performances such as the center frequency and the power consumption of the circuit vary by 5.4% and 11.6%, respectively, for the standard temperature variation.

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.