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An inductorless power converter for low-power energy harvesting is presented. The power converter for energy harvesting is employed to maximize power extraction from energy sources. The power converter is based on a capacitive boost converter which is divided into two stages; a number of first-stage in parallel and shared-stage. The first-stage maximizes power extraction from the energy source while the shared-stage operates as a conventional charge pump. For not only low-power energy source but also high-power energy source, the maximum power extraction is targeted by the proposed converter. The extracted power from energy sources enhances by range from 117% to 161% over the conventional design. The output current of the proposed converter with three first-stages is improved by 183% over conventional converter. The peak efficiencies achieved with three and one first-stage are 53.3% and 38.5% for the proposed and the conventional converters, respectively. The peak end-to-end efficiency is enhanced by 198% as compared to the conventional converter. The proposed inductorless power converter has been implemented on a 0.13μm CMOS process.

Based on the switched capacitor system theory, a new charge pump is designed as the driver of the H-bridge power circuits. The proposed circuit is added with the output feedback control module to realize the steady output, lower the ripple and power noise, and improve the transforming efficiency. Simulation based on 0.35 $\mu \mathrm{\text{m}}$ BCD350GE process demonstrates that the circuit has a ripple voltage as low as 200 mV and reaches a high efficiency up to 70% with a load as much as 20 mA when the supply voltage changes from 8 V to 36 V.

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm² active area in a 0.18 μm CMOS technology.

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V_IN) in all modes with low EMI.

In this paper two low voltage, low power DC–DC converter circuits have been designed with input voltages as low as 290mV to 500mV. Adiabatic technique has been used to reduce power consumption and increase the efficiency of the charge pump of the converters. Boost converter circuits are simulated and the efficiency and power consumption are improved using adiabatic technique. Optimum capacitor bank and rise time–fall time values have been obtained for the adiabatic circuits. Power consumption for the doubler circuit with 310mV input decreases by 67% using adiabatic technique and 0.18$\mu$m CMOS technology parameters.

A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18$\mu$m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5V with 1.8V supply.

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180^∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-$\mu$m CMOS technology with supply voltage of 1.8V. The output clocks with cycle-to-cycle jitter of 2.13ps at 1.6GHz. The phase noise of VCO is $-$137dBc/Hz at an offset of 100MHz and total power consumed by the proposed PLL is 2.63mW at 1.6GHz.

Energy harvesting from the microbial fuel cells have a significant attention in the recent days, due to their cost efficiency, simple designing structure and self-powered system. Also, the emergence of internet of things plays a vital role in many real time application scenarios like agricultural purposes and activities. But, the incorporation of these techniques is one of challenging and interesting tasks in the research field. In the conventional works, the internet of things has been utilized as a cloud storage domain for activating the sensors used for environmental monitoring and controlling purposes. The main intention of this paper is to design a robust and cost-effective sludge water based microbial fuel cells, and utilize it for an internet of things incorporated ecological monitoring and farming applications by activating the smart sensors. It discusses about the various electrode combination with several mixture of substrate to study about the optimum performance of microbial fuel cells. To ease the comparative study, Thing Speak platform is used along with the necessary sensors for continuous monitoring. In addition to that, the efficiency of single and dual chamber microbial fuel cell is analyzed based on the set of parameters such as cost, size, and construction. In this work, the microbial fuel cell-based energy harvesting scheme is also developed with switched capacitance-based metal oxide semiconductor field effect transistor and relay-based charge pump circuit which can be incorporated to the internet of things based agriculture applications. Here, the cost analysis of microbial fuel cell with and without DC–DC converter have been compared for selecting the most suitable one for the application system. Moreover, the digital temperature and humidity sensor can be utilized with the proposed microbial fuel cell system for gathering the inputs of the ecological system, which acts as an interface of the microbial fuel cell and cloud systems. During experimentation, the results of both the energy harvesting schemes are evaluated and compared by using various performance indicators.

Charge pump phase-locked loop(CP PLL) has been widely used in the clocking and data recovery. A high performance design of CP PLL is presented in this paper. It is fabricated in SMIC 0.18μm CMOS process. To reduce noise, the design uses a modified differential charge pump with a large swing, which can effectively inhibit the phase-locked loop output spectrum spurious. A CML oscillator is used, which has lower phase noise and jitter. By changing the difference between the high speed circuit path and low speed circuit path, the delay time of the tuning unit is changed. What’s more, the switched capacitor technology is applied to achieve a wider tuning range. The frequency range of the CP PLL is from 1GHz to 3.1GHz. The phase noise is -107dBc@1MHz and the RMS jitter is 1.725ps at the frequency of 2GHz.

An inductorless power converter for low-power energy harvesting is presented. The power converter for energy harvesting is employed to maximize power extraction from energy sources. The power converter is based on a capacitive boost converter which is divided into two stages; a number of firststage in parallel and shared-stage. The first-stage maximizes power extraction from the energy source while the shared-stage operates as a conventional charge pump. For not only low-power energy source but also high-power energy source, the maximum power extraction is targeted by the proposed converter. The extracted power from energy sources enhances by range from 117% to 161% over the conventional design. The output current of the proposed converter with three first-stages is improved by 183% over conventional converter. The peak efficiencies achieved with three and one first-stage are 53.3% and 38.5% for the proposed and the conventional converters, respectively. The peak end-to-end efficiency is enhanced by 198% as compared to the conventional converter. The proposed inductorless power converter has been implemented on a 0.13μm CMOS process.