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Angular velocity is a very important measurement parameter for autonomous driving and industrial applications. The design of MEMS quartz gyro measurement and control circuit has always been the key to restricting the measurement angular velocity performance of gyro system. This paper introduces the application-specific integrated circuit (ASIC) design and implementation of a MEMS quartz gyro measurement and control circuit for angular velocity measurement. The designed nonlinear multiplier can use a square wave to drive the gyro’s sensitive structure at the beginning of gyro start-up, thereby reducing the gyro power-up time. The drive circuit replaces the PLL with an automatic gain control unit composed of peak detection and proportional integration (PI) controller, which makes the MEMS gyro system have good robustness. First, SIMULINK is used to model and simulate the MEMS gyroscope system-level model, which illustrates the feasibility of the drive circuit design scheme. Then, the operating principle of the drive loop is analyzed, and the design of the key circuit modules of the measurement and control circuit is introduced. Finally, the performance of the gyroscope drive and detection circuit is experimentally tested, the amplitude and frequency uncertainty of the gyroscope drive circuit are evaluated, and the bias instability and nonlinearity of the gyroscope are tested, the experiment results show that the gyroscope has good performance.

Modern communication systems frequently exploit the OFDM (Orthogonal Frequency Division Multiplex) technique to obtain a highly robust transmission of multimedia information, such as digital audio/video broadcast. OFDM and most of the other multimedia compression techniques usually require expensive computations, e.g., FFT (Fast Fourier Transform) and IMDCT (Inverse Modified Discrete Cosine Transform) processing. Traditionally, designing FFT and IMDCT separately involves a significant amount of redundancy in hardware. To reduce the required hardware, this investigation proposes a new ROM-sharing design for storing both FFT twiddle factors and IMDCT coefficients in a DAB (Digital Audio Broadcasting) receiver. We first analyze the correlation between FFT operations and IMDCT operations, and then the combinational logic circuit in the FFT processor is modified such that both IMDCT coefficients and FFT twiddle factors can be obtained simultaneously from a shared ROM. This design can also be applied for computing IFFT (Inverse Fast Fourier Transform) and MDCT for DAB transmitter. Compared with the traditional design using separate module scheme, our design does not need extra ROM for IMDCT/MDCT modules. Therefore, the new scheme offers superior solution for combining high-performance FFT (IFFT) operation and IMDCT (MDCT) operation.

Guaranteeing the stability is one of the most critical issues in designing a variable recursive digital filter. In this paper, we first present an odd-order recursive variable model (transfer function) that is used for designing an odd-order variable-magnitude (VM) digital filter, and then we replace the original coefficients of the denominator of the odd-order transfer function with a set of new parameters. These new parameters can ensure that they can take arbitrary values without incurring instability of the designed odd-order VM filter. To make the VM filter coefficients variable, we find all the VM filter coefficients as polynomial functions of the tuning parameter, which includes two phases. The first phase designs a set of recursive digital filters with fixed coefficients (constant filters), and the second phase utilizes a curve-fitting scheme to represent each coefficient as a polynomial function. As a result, the VM filter coefficients become variable, and the proposed parameter-substitution-based denominator coefficients ensure the filter stability. This is the most important contribution of the parameter-substitution-based design scheme. This paper uses the fifth-order demonstrative example to verify the stability guarantee as well as the design accuracy of the obtained the fifth-order VM filter.

A new cascadable voltage-input, current-output first-order all-pass filter and its applications in second-order filter and oscillator are presented. The proposed circuit employs a single active element namely extra-X current-controlled current conveyor (EX-CCCII) and only a single grounded capacitor. The circuit exhibits high input and high output impedances, so that the filter can be cascaded without additional buffers. The pole frequency is electronically tunable and the circuit requires no component matching constraints. Effects of nonidealities and parasitics are also discussed. As applications, a second-order transadmittance (TA)-mode all-pass filter and a quadrature oscillator are also realized using the proposed voltage-input, current-output first-order all-pass filter. These examples validate easy cascading feature of the proposed circuit. The validity of the proposed circuit is verified through PSPICE simulations using 0.25$\mu$m parameters with a supply voltage of $\pm 1.25$V.

Bandwidth limitation is a vital problem for high-speed data transmission in logging cable telemetry systems (LCTSs). This paper proposes a frequency compensation method with an analog circuit design, possessing high flexibility and robustness. Analytical expressions are derived for the relationship between pole-zero and gain, deviations caused by high temperature; and are then verified via simulation. To address the efficacy of the circuit design, a real case with low computation complexity and high accuracy is proposed and employed. The case of a 7km LCTS shows frequency compensation with a 200% bandwidth expansion — from 160kHz at $-$55dB of the original cable to 300kHz at $-$3dB — and a 60dB improvement in high frequency gain. After comparing the signals with and without compensation, the improvements in transmission performance by the proposed pre-emphasis circuit and equalizer are confirmed.

This paper presents first-order voltage-mode filters using a single current conveyor with an additional X-stage, and passive elements. The new circuits have multifunction capability, and also realize low-shelf, high-shelf and band-shelf functions. The study is carried out on the effects of non-idealities, parasitic elements, and loading on the performance of proposed circuits. Active and passive sensitivities are also analyzed. The active element, extra-X current conveyor used for designing new circuits is simpler than most of the one active element and two passive elements’ based circuits. Detailed comparisons are carried out with relevant available works, and the new circuits are found to be more compact and exhibit higher frequency performances. The simulation results using 0.25$\mu$m CMOS parameters with $\pm$1.25V power-supply are shown to verify the proposed circuits. The proposed circuits are also verified through simulations. Experimental support is given using AD-844 ICs to strengthen the validity of the proposed circuits.

In this paper, we proposed the design and implementation of a new stereoscopic image generation system. In the conventional system, the smoothness of depth map can reduce the incidence of image holes, but cause geometric distortions of the image depth. To solve the problems, the depth map is first refined to increase the accuracy of image depth and the quality of images. Next, we derive a hardware-oriented method for 3D warping and improve hole-filling procedures to enhance the performance of image. Finally, the circuit design is presented according to the proposed stereoscopic image generation system to achieve real-time applications. The experimental results demonstrate that the proposed system can improve by 10–27% when compared to existing methods.

A new approach for realizing sinusoidal signal with quadrature property is proposed, which employs simple analog building blocks and facilitates easy tuning of the oscillation frequency, through a gain factor. The proposed approach is used for realizing a novel quadrature oscillator circuit, which requires three current feedback operational amplifiers and passive components. The proposed circuit provides outputs at low impedance terminals, and benefits from easy control over the frequency of oscillation (FO), which depends on resistive ratio, rather than absolute resistor values. The frequency control is also independent of the condition of oscillation (CO). The nonideal effects and the parasitic studies are presented. The verification of the proposed realization scheme for quadrature oscillators and the new circuit is carried out through both simulation studies and experimental results, using the commercially available chips.

This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the actual inductor which can offset the effect of its DC resistance. In order to verify the generality of the design, the process of designing Lorenz chaotic circuit is given and its attractors can also be observed from the oscilloscope.

This paper introduces a new current-mode approach based configurable analog block (CAB) operating in voltage-mode with high input resistance, employing only three impedances in grounded form and providing a wide range functionality. The fourteen functions realized by the CAB include amplifiers, integrators, differentiators, and filters. The nonideal and parasitic analysis of the proposed configurable block is carried out, along with detailed simulation studies using 0.25$\mu$m CMOS parameters and a supply of $\pm$0.75V for justifying the advance to the field. The active element used for designing the CAB exhibits 1.9 and 0.8GHz as voltage and current transfer bandwidths, respectively, while also providing low output resistance of 105$\mathrm{\Omega }$ in voltage conveying action. Thus, the proposed CAB benefits from high frequency performance and lesser sensitivity to errors due to parasitic at that terminal. Most of the functions utilize beneficial form of grounded components. Presentation of conclusive results for integrator, all-pass filter and band-pass filter is included in form of frequency and transient responses. In-depth intermodulation distortion results for band-pass filter are further given. General conclusive annotations on analog circuit design are made at the end of this study.

Transient modeling analysis of the traditional DC/DC converters shows their worse effect of nonminimum-phase characteristics due to right-half-plane (RHP) zero existence in their plant transfer function. This RHP zero restricts the bandwidth of the switching converters and, that is the main reason for slower response. The motivation of this paper is to present a new technique for eliminating the RHP zero from the dynamics of a conventional boost converter that can solve the problems associated with the nonminimum phase converters and, to focus on its analysis, design and modeling to achieve a high voltage gain as well as the RHP zero cancellation. The proposed technique uses a transformer combined with switching capacitor cells. The striking feature of the suggested topology is its minimum-phase structure, further enhancement of the voltage gain, switching stress reduction, achievement of an improved frequency response and easiness for the design of a closed-loop control scheme to perform the voltage trajectory tracking task. First, the operation of the proposed converter is identified and then, the corresponding circuit performance is evaluated. By using a suitable design, the control-to-output-voltage transfer function is completely free from the RHP zero. The significant advantages of the proposed converter are established via comparisons. To confirm the design approach and theoretical findings, the simulations are introduced and, numerical experimental results such as Bode diagrams are presented.

This paper presents a new polar logic circuit using a single current conveyor, two MOS switches and two resistors in each case. Thus, polar NAND and NOR circuits are proposed. The circuits’ operation details and simulation results are given in support of the proposed theory. The circuits are designed using CMOS CCII$+$ with ±2 V supply voltage. The polar logic levels at the output are −1 and 1 V for logic 0 and 1, respectively. The gates’ functioning for capacitive loading is also tested. The new circuits are expected to be useful in digital and communication systems.

This paper illustrates the recent phenomenon of chaotic beats in a modified version of Chua's circuit, driven by two sinusoidal inputs with slightly different frequencies. In order to satisfy the constraints imposed by the beats dynamics, a novel implementation of the voltage-controlled characteristic of the Chua diode is proposed. By using Pspice simulator, the behavior of the designed circuit is analyzed both in time-domain and state-space, confirming the chaotic nature of the phenomenon and the effectiveness of the approach.

Bifurcation analysis has been applied to many power electronics circuits. Literature abounds with results regarding the various ways in which such circuits lose stability under variation of some selected parameters, e.g. via period-doubling bifurcation, Hopf bifurcation, border collision, etc. The current status of research in the identification of bifurcation behavior in power electronics has reached a stage where the salient types of bifurcation behavior, their underlying causes and the theoretical parameters affecting them have been well understood. Currently, the emphasis of research in this field has gradually shifted toward applications that are of direct relevance to practical design of power electronics. One direction is to apply some of the available research results in bifurcation behavior to the design of practical power electronics circuits. The main difficulty is that the abstract mathematical presentations of the available results are not directly applicable to practical design problems. In this paper we will discuss how research efforts may be directed to bridge this gap.

An original three-dimensional (3D) smooth continuous chaotic system and its mirror-image system with eight common parameters are constructed and a pair of symmetric chaotic attractors can be generated simultaneously. Basic dynamical behaviors of two 3D chaotic systems are investigated respectively. A double-scroll chaotic attractor by connecting the pair of mutual mirror-image attractors is generated via a novel planar switching control approach. Chaos can also be controlled to a fixed point, a periodic orbit and a divergent orbit respectively by switching between two chaotic systems. Finally, an equivalent 3D chaotic system by combining two 3D chaotic systems with a switching law is designed by utilizing a sign function. Two circuit diagrams for realizing the double-scroll attractor are depicted by employing an improved module-based design approach.

In this paper, a novel locally active memristor is constructed. Based on the 3D Hindmarsh–Rose (HR) and 2D FitzHugh–Nagumo (FHN) neuron, a heterogeneous neuronal system is constructed by connecting the two neurons with the locally active memristor. The equilibrium point and stability of the system are investigated. The dynamic behavior of the system is numerically and experimentally revealed by utilizing dynamic analyses in terms of interspike interval bifurcation diagram, two-parameter bifurcation diagram and so on. The unique and abundant dynamic behavior is found in the proposed neuronal system by varying the coupling strength, external stimulus current, memristive parameter and other system parameters. Multiple bursting firing groups in the tongue-shaped domains have been discovered for the first time. Finally, in order to validate the numerical simulation, an analog equivalent circuit of the heterogeneous neuronal system is devised, which demonstrates that the system is physically realizable.

Benefiting from trigonometric and hyperbolic functions, a nonlinear megastable chaotic system is reported in this paper. Its nonlinear equations without linear terms make the system dynamics much more complex. Its coexisting attractors’ shape is diamond-like; thus, this system is said to have diamond-shaped oscillators. State space and time series plots show the existence of coexisting chaotic attractors. The autonomous version of this system was studied previously. Inspired by the former work and applying a forcing term to this system, its dynamics are studied. All forcing term parameters’ impacts are investigated alongside the initial condition-dependent behaviors to confirm the system’s megastability. The dynamical analysis utilizes one-dimensional and two-dimensional bifurcation diagrams, Lyapunov exponents, Kaplan–Yorke dimension, and attraction basin. Because of this system’s megastability, the one-dimensional bifurcation diagrams and Kaplan–Yorke dimension are plotted with three distinct initial conditions. Its analog circuit is simulated in the OrCAD environment to confirm the numerical simulations’ correctness.

Long short-term memory (LSTM) with significantly increased complexity and a large number of parameters have a bottleneck in computing power resulting from limited memory capacity. Hardware acceleration of LSTM using memristor circuit is an effective solution. This paper presents a complete design of memristive LSTM network system. Both the LSTM cell and the fully connected layer circuit are implemented through memristor crossbars, and the 1T1R design avoids the influence of the sneak current which helps to improve the accuracy of network calculation. To reduce the power consumption, the word embedding dimensionality was reduced using the GloVe model, and the number of features in the hidden layer was reduced. The effectiveness of the proposed scheme is verified by performing the text classification task on the IMDB dataset and the hardware training accuracy reached as high as 88.58%.

We propose that genetic encoding of self-assembling components greatly enhances the evolution of complex systems and provides an efficient platform for inductive generalization, i.e. the inductive derivation of a solution to a problem with a potentially infinite number of instances from a limited set of test examples. We exemplify this in simulations by evolving scalable circuitry for several problems. One of them, digital multiplication, has been intensively studied in recent years, where hitherto the evolutionary design of only specific small multipliers was achieved. The fact that this and other problems can be solved in full generality employing self-assembly sheds light on the evolutionary role of self-assembly in biology and is of relevance for the design of complex systems in nano- and bionanotechnology.

Fiber optic gyroscope (FOG) is a new angular rate sensor based on the Sagnac effect. Its stability, reliability and miniaturization are always the research focuses and difficulties. This work applied FPGA to design a circuit for the digital closed loop control system of FOG. The proposed dual closed loop technique improved the zero offset stability of FOG. The using of FPGA brought the digital signal processing by software, the system reliability and agility enhancement as well as the system miniaturization. We also developed some samples of FOG using this design method. The experiments and tests show that the proposed method is efficient and valuable. The stabilities of zero-offsets of all samples are less than 0.075 deg/h.