Narrow Results

Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent fan-out nodes (RFONs) within combinational subcircuits are a major source of topological correlation. We identify two more sources of topological correlation in clocked sequential circuit: sequential RFONs, which are nodes within a clock network where the clock paths to more than one flip-flop branch out; and sequential branch-points, which are nodes within a combinational block where combinational paths to more than one capturing flip-flop branch out. Dealing with all sources of correlation is unacceptably complicated, and we therefore show how to sample a handful of correlation sources without sacrificing significant accuracy in the yield. A further reduction in computation time can be obtained by sampling only those nodes that are likely to affect the yield. These techniques are applied to yield analysis using statistical static timing analysis based on discrete random variables and also to yield analysis based on Monte Carlo simulation; the accuracy and efficiency of both methods are assessed using example circuits. The sequential RFONs suggest that timing yield may be improved by optimizing the clock network, and we address this possibility.

Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gating (CG) has been proposed for finite state machines (FSMs). The CG logic is based on the idea of dynamically disabling the clock signal to the sequential blocks of the FSM during periods of inactivity. The inactive state is decided by the occurrence of self-loops within the FSM. The proposed gating technique operates at a fine level of granularity and can be generally implemented to any FSMs. A technique of partitioning the registers of the FSM is introduced in this work in order to avoid functional errors and signal losses during gating. The logic of registers partitioning for CG in large FSMs containing few or no self-loops is also presented in this work. The simulation results obtained shows up to 38% (max) dynamic power reduction of the FSM with a little penalty in area. The timing slack associated with the gated and non-gated FSMs is also analyzed for varying clock frequencies. The results indicate a minimal increase in delay after gating. The technique for CG in large FSMs containing few or no self-loops has yield up to 58% (max) power reduction.