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HIGH-SPEED ARCHITECTURES AND BUILDING BLOCKS FOR CLOCK AND DATA RECOVERY SYSTEMS
Preview AbstractThis paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.
HIGH-SPEED ARCHITECTURES AND BUILDING BLOCKS FOR CLOCK AND DATA RECOVERY SYSTEMS
Preview AbstractThis paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.