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In this paper, we propose a three-port circulator circuit based on operational transconductance amplifiers (OTAs) that features a resistorless topology, categorizing it as a type-A circulator. The behavior of the proposed structure is analyzed in the presence of OTA nonidealities, with corresponding mathematical formulations presented. The functionality of the circuit is verified through SPICE simulations using 180nm CMOS technology parameters. We also examine the circuit’s performance across various process corners, as well as under supply and temperature variations, finding that the port behavior remains consistent. Additionally, the impact of process variation is assessed through Monte Carlo simulations comprising 100 runs, revealing that the circuit exhibits minimal sensitivity, with the mean frequency at port 2 being 1.006MHz and a standard deviation of 493Hz. The linearity of the proposed circuit is evaluated, showing a total harmonic distortion (THD) variation of less than 2%.

A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.

Negative impedance converter circuits (NICs) are important building blocks in design and manufacturing of analog and mixed mode integrated circuits. In this paper, a catalogue of single-current feedback amplifier-based negative impedance converter circuits having impedance scaling properties is proposed. Various examples are presented to illustrate the versatility of the proposed NIC circuits.

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

This paper presents an electronically tunable current-mode first-order universal filter. The proposed circuit employs only a single Extra-X Current-Controlled Conveyor (EX-CCCII) and a single grounded capacitor, which is suitable for IC implementation. The circuit can realize three current transfer functions simultaneously, namely low-pass, high-pass and all-pass. The proposed circuit exhibits low-input and high-output impedance, which is suitable for cascading. The pole frequency of the filter can be electronically tuned, by varying the bias current of EX-CCCII. The nonidealities and parasitic effects on the circuit performance are investigated in detail. Also, the Monte Carlo analysis is done to show the effect of active and passive element mismatches on the pole frequency. An eight-phase current-mode sinusoidal oscillator and current-mode second-order filter are further realized using the proposed circuit. The functionality of the proposed circuits is verified through PSPICE simulations, using 0.25-$\mu$m TSMC CMOS technology parameters.

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35$\mu$m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided.

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included.

This paper presents a modified Current Follower Transconductance Amplifier (CFTA). It provides the essential features of high transconductance, wide bandwidth besides a wide linear range. It records the highest transconductance of 18.2mS and power dissipation of 1.12mW. Moreover, the linear range ($i_F$ versus $i_x$) of CFTA is found as $\pm 80$$\mu$A. All these essential performance parameters are found much better than the available literature. As an application, a novel second-order universal filter is implemented using the proposed CFTA. It is found that the performance of the filter improves with the use of the proposed CFTA.

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations.

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

In this study, a novel DDCC-based two-integrator-loop universal active-C biquad with a companding process scheme is proposed. The proposed filter employs some processing blocks such as integrators and summing blocks. The use of the block diagram design procedure is attractive and systematic. The state space synthesis technique is utilized for the topology of the integrator design. Several advantages of the proposed filter are briefly expressed as: simultaneously realizing five second-order filter functions such as low-pass, high-pass, band-pass, all-pass and notch filter responses; offering resistorless realization; dissipating low power; having electronic tunability feature of its pole frequency and quality factor orthogonally; not suffering from disadvantages of the passive element matching problems. Some simulation results including frequency and time domain analysis results by using the PSpice program are carried out to confirm the theoretical ones. All the obtained simulation results are discussed.

An adaptive biased architecture of voltage differencing transconductance amplifier (AB-VDTA) with high transconductance gain is proposed in this paper. The proposed AB-VDTA is very efficient in terms of power. The structure proposed involves of two units namely two transconductance amplifiers (TAs) and two squarer. The bias current of the TA is made to vary with a square relation of the differential input voltage. Therefore, the proposed structure provides tunable gain depending on the input differential voltage. The proposed AB-VDTA exhibits improved transconductance gain, transient characteristics, reduced standby power dissipation and linearity for large range of inputs. The mathematical formulation has been presented to establish the characteristics of the proposed AB-VDTA. The proposed structure of AB-VDTA is validated through SPICE simulations using 180nm complementary metal oxide semiconductor (CMOS) technology. The proposed scheme has an edge over the existing ones as the outlined methods enhance the transconductance gain by increasing the bias current. The $g_{m1}$ values are observed to be 2.3 and 1.4mS for proposed AB-VDTA and conventional VDTA, respectively, with the corresponding 3dB frequencies 620 and 348MHz. Therefore, 64% improvement in transconductance gain is recorded for same value of bias currents. The linear input range of TA1 is observed to be $\pm 150$mV and the overall linear range of the VDTA is $\pm 100$mV for the proposed AB-VDTA. The PVT analysis is carried out to show the effect of process corners. To check the robustness of the proposed VDTA, Monte Carlo analysis is performed, and results have been included in the form of histograms. As an application example, a current mode (CM) universal single input multiple output (SIMO) biquad filter is also designed using the proposed VDTA to show its usefulness, and a 2.7 times higher pole frequency is obtained at equal bias current.

To minimize circuit design, a novel current-mode wave active filter (WAF) employing the extra-X current-controlled current conveyor transconductance amplifier (EX-CCCCTA) active building block (ABB), is presented in this paper. Unlike other WAFs in the research, this design uses a single EX-CCCCTA, and grounded passive components suitable for monolithic integration, and an electronic tuning capability to offer an appropriate response at high frequencies up to 10MHz approximately. Compared to their passive equivalents, active filters have tunable gain, monolithic integration compatibility, and appropriate input–output impedance. Furthermore, Monte Carlo analysis, total harmonic distortion (%THD), and noise analysis are used to validate the filter performances. The SPICE simulations verify the functional effectiveness of the proposed WAF.