Narrow Results

This paper presents a new design of half-static clock-gating D-type flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 μm CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures.

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12$\mu$m² and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.