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This paper presents a design and implementation of a wireless data acquisition/transmitting system for Euro-balise. The presented system contains three parts: a power signal generator, a receiver and a transmitter. We also propose an all-digital coherent-like frequency shift keying (FSK) demodulator for the receiver of the system. The proposed demodulator based on the use of multi-bit XOR gates and a mean value filter can improve bit error ratio (BER) performance without increasing obvious complexity. Differential bi-phase level (DBPL) coding is adopted to ensure the reliability of the transmitter. The FSK demodulator and DBPL coder was implemented on field programmable gate array (FPGA). Hardware test results show that the equipment based on the presented system has good application in reading and writing data of the Euro-balise.

This paper proposes a high data rate, low-power, low-voltage design of OTA-based M-ary ASK, FSK and QAM modulator and demodulator circuits. Conventional D/A converter of M-ary circuit has been replaced with the operational transconductance amplifier-based n-bits to 2ⁿ level converter which operates with input frequencies up to 2.1 GHz. OTA-based oscillator and PLL is being designed for high speed M-ary FSK. Eye diagram analysis has been carried out, conforming a very low signal distortion. Theoretical analysis of bit error rate has been done. The circuit analysis and simulation results confirm the reliability and accuracy of the design. Effective layouts and die photographs of the proposed designs are also presented.

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-$\mu$W.

Implantable biomedical devices (IBDs) play a vital role in today’s healthcare industry. Such applications demand high data rate, low power and small-sized demodulators. This work presents a simple small-sized low-power architecture for differential quadrature phase shift keying (DQPSK) demodulator for these devices. The proposed circuitry is designed in UMC 90-nm CMOS technology and occupies a layout area of 0.015mm². It is operated at 1-V supply voltage with a power consumption of 405$\mu$W. The carrier frequency is 10MHz and the obtained data rate is 20Mbps. Hence it exhibits a high data-rate-to-carrier-frequency (DRCF) ratio of 200% making it ideal for IBDs.