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Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12$\mu$m² and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

With the new age of technology and the release of the Internet of Things (IoT) revolution, there is a need to connect a wide range of devices with varying throughput and performance requirements. In this paper, a digital transmitter of NarrowBand Internet of Things (NB-IoT) is proposed targeting very low power and delay-insensitive IoT applications with low throughput requirements. NB-IoT is a new cellular technology introduced by 3GPP in release 13 to provide wide-area coverage for the IoT. The low-cost receivers for such devices should have very low complexity, consume low power and hence run for several years. In this paper, the implementation of the data path chain of digital uplink transmitter is presented. The standard specifications are studied carefully to determine the required design parameters for each block. And the design is synthesized in UMC 130-nm technology.

This paper studies the capability of digital architecture to mimic fractal behavior. As chaotic attractors realized digitally had opened many tracks, digital designs mimicking fractals may ultimately achieve the same. This study is based on a complex single-dimensional discrete chaotic system known as the generalized positive logistic map. The fractals realized from this system are linked to the results of the mathematical analysis to understand the fractal behavior with different variations. A digital hardware architecture manifesting the fractal behavior is achieved on FPGA, showing a fractal entity experimentally. With this digital realization, it is hoped that fractals can follow the example of chaotic attractors digital applications.

General functional decomposition is mainly perceived as a logic synthesis method for implementing Boolean functions into FPGA-based architectures. However it also has important applications in many other fields of modern engineering and science.

In this paper, advantages of functional decomposition are demonstrated on "real life" examples. Application of decomposition-based methods in other fields of modern engineering is presented. In the case of decision tables, application of decomposition methods leads to significant benefits in the analysis process of data dependencies, especially in cases when the input decision tables are unmanageably large. Experimental results demonstrate that it can help implementing sequential machines using flip-flops or ROM memory. It also can be efficiently used as multilevel logic synthesis method for VLSI technology.

The most promising emerging technology that can reduce the power, area and delay in digital circuits is Quantum-dot Cellular Automata (QCA) technology. The Serial Input-Serial Output (SISO) Shift Register (SR) is a basic component in digital circuits. The SISO SR can be designed using two methods in the QCA technology, directly mapping circuits from the CMOS technology and using the inherent capability of the QCA technology. This paper presents and evaluates the new $n$-bit QCA SISO SR that not only uses the inherent capability of QCA technology but also has a regular architecture. The proposed $n$-bit SISO SR is developed based on the building block, which is designed in this paper. In addition, the developed QCA SISO SR has coplanar architecture and it has the ability to correct or change data. The proposed $n$-bit SISO SR is evaluated for 3, 4 and 5 bits using QCADesigner-$E$. The results demonstrate that the designed circuits for 3-, 4- and 5-bit QCA SISO SRs require 68 (0.06 $\mu$m${}^2)$, 92 (0.08$\mu$m${}^2)$ and 116 (0.09$\mu$m${}^2)$ cells (area), respectively. The comparison demonstrates that the developed QCA SISO SRs have advantages in comparison to other QCA SISO SR circuits.

This paper presents a general 3D method to simulate a rotting process in fruits using a visual model for the digital design of the fruits. The global rot parameter and rot resistance parameter are used to control a dynamic simulation of a rotting process. The rot resistance parameters of every point of a 3D fruit model are generated by an interactive designing method that is similar to the traditional sketch drawing tools. We construct a texture of a rot region on a fruit surface by resistance parameters. The degree of rot that is used to control both shape and appearance of rotten fruit surface can be computed by tuning the resistance parameters and global rot parameters. We derive an exponential function to calculate the depression displacement of geometric shape caused by the rot. In order to render a wrinkle on the rot region, we use a normal noise map to modify a normal vector of fruit model and use an isotropic ward BRDF model to represent an appearance of fruit in which the time-varying diffuse reflectance is derived from the real photos. We utilize a linear function to control the dynamic simulation processes including shape deformation and aging appearance. We have evaluated our method by simulating the rotten apple and moldy orange. The results have shown that our method provides a dynamic, real-time and realistic simulation, and it is flexible, fast and of a general character for digital fruit design as a visualization model.

This paper tries to investigate the change of social use of space due to complex shape buildings design. The chances of conceiving free form architectural space in recent years have been drastically increased by the opportunities offered by the current means of digital design. The ultimate goal of this research, however, goes far beyond the intentions of the individual and his understanding requires collective forms of ownership. It is inevitable to ask what types of habitat could result from these scenarios, how are we changing social use of spaces? This paper tries to give some answers to these questions.

Assembly model is the key information applied in 3D design software. The information of the character, hierarchical and assembly relationship of assembly model are discussed. And the expression method of component information model and storage model are established. The relationship of the components should content not only the assembly information but also the function information in order to help the designers for problem solving. The mapping library for assembly relationship and function relationship is founded in order to support the component analysis. Knowledge model of the component is realized by object-oriented method. As an example, the function relationship of a tug-of-war robot is gotten based on the assembly model of it in Solidworks. The efficiency of the knowledge model for the inventive problem solving is illustrated.

This paper takes a local furrow opener as the research object. The working performance of this furrow opener has been studied by test and simulation using the discrete element method and EDEM software. On this basis, the effects of working speed and operating depth of furrow operating on tillage forces are studied by simulation analysis. Good agreement has been found between the numerical results and experimental data and the relative errors are within 10%~15%. The feasibility and effectiveness of analysing the furrow operating process using DEM are validated.