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In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.

In this paper, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for non-speed-critical large capacitive loading applications is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer's output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer. Moreover, the overall power dissipation of the proposed buffer is further decreased by optimizing the number of tapered stages and the values of tapered factors in the tapered chains of the short-circuit power eliminating circuit. In order to validate the efficiency of the proposed design, theoretical analysis and simulations with various capacitive loads are conducted using TSMC 0.18-μm 1P6M and UMC advanced 90-nm 1P9M CMOS technologies. The results show that the power dissipation of the proposed two-phase CMOS buffer is 8.6% lower than that of the conventional two-phase CMOS tapered buffer. The power-delay product of the proposed buffer is 2.7% smaller than that of the conventional tapered buffer.

Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gating (CG) has been proposed for finite state machines (FSMs). The CG logic is based on the idea of dynamically disabling the clock signal to the sequential blocks of the FSM during periods of inactivity. The inactive state is decided by the occurrence of self-loops within the FSM. The proposed gating technique operates at a fine level of granularity and can be generally implemented to any FSMs. A technique of partitioning the registers of the FSM is introduced in this work in order to avoid functional errors and signal losses during gating. The logic of registers partitioning for CG in large FSMs containing few or no self-loops is also presented in this work. The simulation results obtained shows up to 38% (max) dynamic power reduction of the FSM with a little penalty in area. The timing slack associated with the gated and non-gated FSMs is also analyzed for varying clock frequencies. The results indicate a minimal increase in delay after gating. The technique for CG in large FSMs containing few or no self-loops has yield up to 58% (max) power reduction.