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A 3D model of flip-chip package is established and thermal–electrical coupling is analyzed. The effect of the width of Aluminum (Al) trace on electro-migration mechanism is also studied. Reducing rates of the hot-spot temperature, the max Joule heating, the max temperature gradient and the max current density are defined to research the effects of the Al trace thickness and the UBM thickness on electro-migration.

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

A 3D model of FCBGA is established, and the thermal-electrical coupling is simulated. The distribution of temperature, current density, temperature gradient, Joule heating under thermal-electrical coupling in solder bump is achieved. Effect of passivation layer opening dimension on electro-migration mechanism is analyzed, and current density evenness is defined to measure the degree of current density unbalance.