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This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process.

This paper proposed an energy efficient adder employing multistage latency and approximate computing technology. The delay of the adder decreases after the critical path of the adder is divided into multiple short stages with series of predictors, then the approximate computing technology is exploited to make a tradeoff between output quality and energy efficiency. The proposed design is applied into discrete cosine transformation (DCT) in image processing and support vector machine (SVM) algorithm in machine learning to verify its availability, the simulation results demonstrate that the proposed approximate adder provides 25.6% power-delay-product (PDP) reduction and 2 orders of magnitude reduction in output error than the recent counterpart designs. Compared with the conventional accurate ripple carry adder (RCA) and Kogge stone adde (KSA), the proposed design presents 66.5% to 37.6% PDP reduction, at the cost of negligible output quality reduction, which are qualified as peak signal-to-noise ratio (PSNR) for DCT (decreases from 33.88dB to 33.84dB) and classification accuracy for SVM (decreases from 80.46% to 79.19%).

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

Recently developed spin-based, racetrack memory (RM) shows great promise in enabling nonvolatile memory with unprecedented density and energy efficiency. RM-based technology will leverage the power and cost limit of main memory. However, main memory has random accessing patterns and makes racetrack shifting overhead variable that induces an unstable latency. This paper analyzes the shifting features in view of computing architecture by exploring the design space of RM. We propose RM-based pre-shifting and direction optimized policies to reduce the shifting overhead and to achieve a DRAM comparable performance without additional energy and area overhead. Experiments with a wide range of SPEC2006 benchmarks show the proposed methodology outperforms RM-based main memory without pre-shifting by 12% in energy consumption. Compared to DRAM-based main memory of the same capacity, the proposed methodology improves the energy consumption by 53% on average.

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45nm and 180nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45nm result shows that the comparator has the total delay as low as 104.3ps and consumes only 0.288fJ of energy per conversion from a 0.8V supply. The mean value of input voltage error due to kickback noise is found as 306nV.

The applications of wireless sensor network (WSN) are growing very rapidly, so utilizing the energy in an efficient manner is a challenging task as the battery life of nodes in WSN is very limited. For enhancing the lifetime of the network, various clustering protocols have been proposed earlier. In this paper, a clustering protocol named Energy Efficient Clusterhead Selection Scheme (ECSS) is proposed. The proposed ECSS protocol focusses on selecting an energy-efficient cluster head (CH), which helps in enhancing the overall lifetime and performance of the network. The proposed ECSS protocol uses the energy levels of nodes for the CH selection process. The proposed protocol is designed for the heterogeneous environment and it aims in minimizing the energy usage in the network and thereby improving the lifespan of the network. To measure the performance of the proposed ECSS protocol, the comparison is performed with the various existing protocols using MATLAB simulator. The results of simulation show that the proposed ECSS protocol has enhanced the network lifespan, throughput, and energy usage of the network as contrasted to the existing protocols.

Consuming energy at the maximal level is a major concern in wireless sensor networks (WSNs). Many researchers focus on reducing and preserving the energy. The duration of active network of WSNs is affected by energy consumption of sensor nodes. For typical applications such as structure monitoring, border surveillance, integrated into the external surface of a pipeline, and clambered along the sustaining structure of a bridge, sensor node energy efficiency is an important issue. The paper proposed an energy-efficient multi-hop routing protocol using hybrid optimization algorithm (E²MR-HOA) for WSNs. The proposed routing protocol consists of two algorithms, i.e., hybrid optimization algorithm. We present modified chemical reaction optimization (MCRO) algorithm to form clusters and select cluster head (CH) among the cluster members. Then the modified bacterial forging search (MBFS) algorithm is used to compute reliable route between source to destination. The proposed E²MR-HOA protocol is evaluated using NS2 simulations. The simulation result shows that the proposed routing protocol provides significant energy efficiency with network lifetime over the existing routing protocols.

Wireless sensor networks (WSNs) are commonly used for continuous monitoring applications. However, due to remote and inaccessible WSN deployments, the batteries cannot be easily replaced. As a result, the quality of sensor monitoring changes with respect to time. We investigate the rate of change in coverage as sensor nodes are depleted of their energy resources. In this paper, we propose a coverage analysis method which not only focuses on the coverage itself but also on its uniformity and efficiency. The paper documents interesting network coverage evaluation studies showing several ways of getting valuable information about a WSN's coverage's uniformity and efficiency by appropriately interpreting the change in its efficient and redundant coverage ratios (efficient and redundant coverage ratios are terms defined in this paper). We also specify the particular WSN applications where the proposed coverage analysis method will be more suitable.

In this paper we discuss minimum energy broadcast routing with directional antennas in ad hoc and sensor networks. We assume that the network consists of sensor nodes whose antennas are switched beam directional antennas. The problem of our concern is: a given set V with n nodes and each node v_i has l(i) transmission directions (i.e. the antenna sectors) and a broadcast request sourced at s, how to find a broadcast tree rooted at s and spanning all nodes in V such that the total energy is minimized. This problem involves with the choice of transmitting nodes and their transmission directions, which is NP-hard. We firstly propose a directed Steiner tree-based approximation algorithm for this problem and discuss its distributed implementation. Then we also propose a |V|-approximation algorithm and one heuristic with lower time complexities. Extensive simulations have demonstrated the efficiency of our algorithms.

The need of weight reduction, not only in passenger cars, due to the tightened CO2 regulations, leads to an increasing trend of using different Aluminium alloys (6xxx, 7xxx) for producing car body components. In order to be able to form complex shaped parts, to decrease spring back and to increase the material properties of the formed part, the technology Aluminium Hot Form Quench (HFQ^®) seems to be an adequate solution. Since this process has similarities to Press Hardening of Boron steel, it is interesting to see what has to be adopted in order to be able to integrate this technology into the press shop. Furthermore it is interesting to compare Aluminium HFQ^® with other advanced Aluminium forming technologies, in order to find out which solution is the most suitable one, to be able to produce complex shaped high strength components. Within this paper AP&T shows a sample of how to set up an Aluminium HFQ^® production line cost and energy efficient.

This paper presents a competition-based clustering routing scheme, CCH, for Wireless Sensor Networks, in which energy efficiency is the most important factor. In CCH every node has a cluster head power value according to their position and residual energy. All nodes in the same cluster compete with each other by the cluster head power value to become a cluster head. The CCH uses rounds to select cluster heads and transmit data, while the cluster is constructed by the base station and cannot be changed. When a cluster head is selected, all nodes in the cluster know which will be the next cluster head in recent N rounds according to the combat log table. This methodology improves the efficiency of choosing cluster head and of communications between cluster heads and the base station.