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This paper presents the evolution of combinational logic circuits by a new hybrid algorithm known as the Differential Evolution Particle Swarm Optimization (DEPSO), formulated from the concepts of a modified particle swarm and differential evolution. The particle swarm in the hybrid algorithm is represented by a discrete 3-integer approach. A hybrid multi-objective fitness function is coined to achieve two goals for the evolution of circuits. The first goal is to evolve combinational logic circuits with 100% functionality, called the feasible circuits. The second goal is to minimize the number of logic gates needed to realize the feasible circuits. In addition, the paper presents modifications to enhance performance and robustness of particle swarm and evolutionary techniques for discrete optimization problems. Comparison of the performance of the hybrid algorithm to the conventional Karnaugh map and evolvable hardware techniques such as genetic algorithm, modified particle swarm, and differential evolution are presented on a number of case studies. Results show that feasible circuits are always achieved by the DEPSO algorithm unlike with other algorithms and the percentage of best solutions (minimal logic gates) is higher.

The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-tolerant system is really a real-time system, and the recovery time is necessary in fault detection and recovery. However, when applying EHW, real-time characteristic is usually ignored. In this paper, a fault-tolerant strategy based on EHW is proposed. The recovery time, predicted by the fault tree analysis (FTA), is considered as a constraint condition. A configuration library is set up in the design phase to accelerate the repair process of the anticipated faults. An evolvable algorithm (EA) based on similarity is applied to evolve the repair circuit for the unanticipated faults. When the library reaches the upper, the target system is reconfigured by the EA-repair technology. Extensive experiments are conducted to show that our method can improve the fault-tolerance of the system while satisfying the real-time requirement on FPGA platform. In a long run system, our method can keep a higher fault recovery rate.

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

The use of Genetic Algorithms (GAs) to evolve Continuous Time Recurrent Neural Networks (CTRNNs) for locomotion control of a hexapod robot was demonstrated in previous work. Those controllers were shown to be robust to loss of sensory information and other peripheral variations and their operation was explained through qualitative dynamical systems analysis. Although real robot controllers were fielded, our prior methods contained drawbacks limiting the attractiveness of their implementation as real devices. These included centralization of the evolutionary learning algorithms and the inability of those algorithms to evolve effective controllers without inclusion of a priori architectural knowledge. In this paper, we will introduce a generic neuromorphic Evolvable Hardware (EH) learning architecture and show how it can be used to overcome these previous difficulties. We will also introduce a novel modification to previously reported EH methods that improves search efficacy. We will discuss our previous work, introduce relevant concepts from the emerging field of evolvable hardware as well as our chip, and show how it can be used to deliver effective and practical locomotion control. We will focus especially on the integrated systems abilities to self-heal and reconfigure while in service and will examine centralized, decentralized, and hybrid learning configurations.