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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

This paper proposes a novel method which is based on particle swarm optimization (PSO) algorithm for the two-dimensional FIR digital filter design. In the PSO algorithm, it simply uses two adjusting mechanisms including particle’s velocity and position updating to achieve the optimization. In addition, numerical representations for each candidate solution are completely real numbers. The PSO algorithm is utilized to design the two-dimensional FIR digital filter with linear-phase characteristic so that its frequency response can approximately meet the desired specification. Finally, we will illustrate the design performance of the proposed method with two experiments. Simulation results reveal that the proposed scheme has a good design performance on the two-dimensional FIR digital filter.