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This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D²-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.

During the past decades, computer science experts were inspired from the study of biological organisms. Moreover, bio-inspired algorithms were produced that many times can give excellent solutions with low computational cost in complex engineering problems. In our case, the plasmodium of Physarum polycephalum is capable of finding the shortest path solution between two points in a labyrinth. In this study, we implement a Cellular Automata (CA) model in hardware, which attempts to describe and, moreover, mimic the behavior of the plasmodium in a maze. Beyond the successful implementation of the CA-based Physarum model in software, in order to take full advantage of the inherent parallelism of CA, we focus on a Field Programmable Gate Array (FPGA) implementation of the proposed model. Namely, two different implementations were considered here. Their difference is on the desired precision produced by the numerical representation of CA model parameters. Based on the corresponding results of the shortest path in the labyrinth,the modeling efficiency of both approaches was compared depending on the resulting error propagation. The presented FPGA implementations succeed to take advantage of the CA's inherit parallelism and improve the performance of the CA algorithm when compared with software in terms of computational speed and power consumption. As a result, the implementations presented here, can also be considered as a preliminary CA-based Physarum polycephalum IP core which produces a biological inspired solution to the shortest-path problem.

Not only in the field of high-performance computing (HPC), field programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to central processing units (CPUs) or even graphics processing units (GPUs), adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096$\times$4096 and solution on the coarsest using the conjugate gradient (CG) method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

Filtered-x Least Mean Squares (FxLMS) is an algorithm commonly used for Active Noise Control (ANC) systems in order to cancel undesired acoustic waves from a sound source. There is a small number of hardware designs reported in the literature, that in turn only use one reference signal, one error signal and one output control signal. In this paper, it is proposed a 3-dimensional hardware-based version of the widely used FxLMS algorithm, using one reference microphone, 18 error microphones, one output and a FIR filter of 400${}^{th}$ order. The FxLMS algorithm was implemented in a Xilinx Artix 7 FPGA running at 25 MHz, which allowed to update the filter coefficients in 32.44$\mu$ s. The main idea behind this work is to propose a pipelined parallelized architecture to achieve processing times faster than real time for the filter coefficients update. The main contribution of this work is not the ANC technique itself, but rather the proposed hardware implementation that utilizes integer arithmetic, which provided an acceptable error when benchmarked with a software implementation. This parallel system allows a scalable implementation as an advantage of using FPGA without compromising the computational cost and, consequently, the latency.

This paper proposes a real-time super-resolution (SR) system. The proposed system performs a fast SR algorithm that generates a high-resolution image from a low-resolution image using direct regression functions with an up-scaling factor of 2. This algorithm contained two processes: feature learning and SR image prediction. The feature learning stage is performed offline, in which several regression functions were trained. The SR image prediction stage is implemented on the proposed system to generate high-resolution image patches. The system implemented on a Xilinx Virtex 7 field-programmable gate array achieves output resolution of $3840\times 2160$ (UHD) at 85 fps and 700Mpixels/s throughput. Structure similarity (SSIM) is measured for image quality. Experimental results show that the proposed system provides high image quality for real-time applications. And the proposed system possesses high scalability for resolution.

There has been a growing interest from academia and industry in developing circuits and systems for edge computing and quality control tasks in food production lines, where image-processing is frequently required. This paper outlines the required considerations for designing a fruit classification system based on image-processing using Cellular Automata (CA) models and integrating it into reconfigurable hardware (HW) such as Field Programmable Gate Arrays (FPGAs). Parallel processing in CA requires numerous processing elements to be implemented and mapping CA models to HW generally comes with limitations. Homogeneous CA arrays are easier to design and implement in HW but can be resource-demanding. To fill this gap, this study explores different alternatives for the HW implementation of CA models, particularly trading computational-parallelism for a more optimized use of the available HW resources. We conducted experimental tests of the designed HW system using the Digilent Nexys development board, and the operation was validated against software-based benchmarks for image-processing, particularly concerning edge-detection. The presented study provides a broader range of design solutions for the HW implementation of two-dimensional CA models and a better understanding of their advantages and disadvantages. The results show that solutions focusing on instruction-parallelism add some complexity to the conception and require more design effort, compared to homogeneous CA models composed of identical cells. However, the instruction-parallel design solutions can significantly improve the HW resource utilization, especially when implementing computationally intensive CA rules in FPGAs.