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The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time.

This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except $X_i\cdot Y_i$ and $X_i\cdot Z_i)$ operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.

Evaluating and benchmarking software and hardware field programmable gate array (FPGA)-based digital watermarking are considered challenging tasks because of multiple and conflicting evaluation criteria. A few evaluation and benchmarking techniques/frameworks have been implemented to digital watermarking or steganography; however, these approaches still present certain limitations. In particular, fixing some attributes on account of other attributes and well-known benchmarking approaches are limited to robust watermarking techniques. Thus, this study aims toward a new methodology for evaluation and benchmarking using multi-criteria analysis for software and hardware “FPGA”-based digital watermarking or steganography. To achieve this objective, two iterations are conducted. The first iteration consists of two stages: discussing software and hardware “FPGA”-based digital watermarking or steganography to create a dataset with various samples for benchmarking and discussing the evaluation method and then discussing the test for software and hardware “FPGA”-based digital watermarking or steganography according to multi-criteria evaluation (i.e., complexity, payload and quality) to create a decision matrix. The second iteration applies different decision-making techniques (i.e., SAW, MEW, HAW, TOPSIS, WSM and WPM)) to benchmark the results of the first iteration (i.e., software or hardware FPGA-based digital watermarking or steganography approaches). Then, the discussed mean, standard deviation and paired sample $t$-test results are used to measure the correlations among different techniques based on the ranking results. The discussion findings are described as follows: (1) the integration of developer and evaluator preferences into the evaluation and benchmarking for software and hardware FPGA-based digital watermarking or steganography, (2) the process of assigning weights and (3) visualizing large-scale data sample in either software or hardware FPGA-based digital watermarking or steganography algorithms.

Due to their structure and complexity, chaotic systems have been introduced in several domains such as electronic circuits, commerce domain, encryption and network security. In this paper, we propose a novel multidimensional chaotic system with multiple parameters and nonlinear terms. Then, a two-phase algorithm is presented for investigating the chaotic behavior using bifurcation and Lyapunov exponent (LE) theories. Finally, we illustrate the performances of our proposal by constructing three (03) chaotic maps (3-D, 4-D and 5-D) and implementing the 3-D map on Field-Programmable-Gate-Array (FPGA) boards to generate random keys for securing a client–server communication purpose. Based on the achieved results, the proposed scheme is considered an ideal candidate for numerous resource-constrained devices and internet of the things (IoT) applications.

Blind source separation (BSS) is the process of extracting sources from mixed data without or with limited awareness of the sources. This paper uses field programmable gate array (FPGA) to create an effective version of the Blind source separation algorithm (ICA) with a single Multiply Accumulate (MAC) adaptive filter and to optimize it. Recently, space research has paid a lot of attention to this technique. We address this problem in two sections. The first approach is ICA, which seeks a linear revolution that can enhance the mutual independence of the mixture to distinguish the source signals from mixed signals. The second is a powerful flexible finite impulse response (FIR) filter construction that makes use of a MAC core and is adaptable. The adjustable coefficient filters have been used in the proposed study to determine the undiscovered system utilizing an optimal least mean square (LMS) technique. The filter tap under consideration in this paper includes 32 taps, and hardware description language (HDL) and FPGA devices were used to carry out the analysis and synthesis of it. When compared to the described architecture, the executed filter architecture uses 80% fewer resources and increases clock frequency by nearly five times, and speed is increased up to 32%.

In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for pseudo-random bit generation is proposed to improve the speed of the generator and minimize power dissipation with the optimum chip area. To improve its performance, a new pseudo-random bit generator (PRBG) employing two-operand modulo adder and without shifting operation-based dual-CLCG architecture is proposed. The novelty of the proposed dual-CLCG architecture is the designing of LCG based on two-operand modulo adder rather than a three-operand one and without using shifting operation as compared to the existing LCG architecture. The aim of the work is to generate pseudo-random bits at a uniform clock rate at the maximum clock frequency and achieve maximum length of the random bit sequence. The power dissipation with the optimum chip area of PRBG is also observed for the proposed architecture. The generated sequence passes all the 15 tests of the National Institute of Standards and Technology (NIST) standard. Verilog HDL code is used for the design of the proposed architecture. Its simulation is done on commercially available Spartan-3E FPGA (ISE Design Suite by Xilinx) as well as on 90-nm CMOS technology (Cadence tool).

In the currently accepted model for cosmic baryon evolution, Cosmic Dawn (CD) and the Epoch of Reionization (EoR) are significant times when first light from the first luminous objects emerged, transformed and subsequently ionized the primordial gas. The 21cm (1420MHz) hyperfine transition of neutral hydrogen, redshifted from these cosmic times to a frequency range of 40MHz to 200MHz, has been recognized as an important probe of the physics of CD/EoR. The global 21cm signal is predicted to be a spectral distortion of a few 10’s to a few 100’s of mK, which is expected to be present in the cosmic radio background as a trace additive component. Shaped Antenna measurement of the background RAdio Spectrum (SARAS) is a spectral radiometer purpose designed to detect the weak 21cm signal from CD/EoR. An important subsystem of the radiometer, the digital correlation spectrometer, is developed around a high-speed digital signal processing platform called pSPEC. pSPEC is built around two quad 10-bit analog-to-digital converters (EV10AQ190) and a Virtex 6 (XC6VLX240T) field programmable gate array, with provision for multiple Gigabit Ethernet and 4.5Gbps fiber-optic interfaces. Here, we describe the system design of the digital spectrometer, the pSPEC board, and the adaptation of pSPEC to implement a high spectral resolution (61kHz), high dynamic range ($10^5$:1) correlation spectrometer covering the entire CD/EoR band. As the SARAS radiometer is required to be deployed in remote locations where terrestrial radio frequency interference (RFI) is a minimum, the spectrometer is designed to be compact, portable and operating off internal batteries. The paper includes an evaluation of the spectrometer’s susceptibility to RFI and capability to detect signals from CD/EoR.

Radio Frequency Interference (RFI) excision in wideband radio telescope receivers is gaining significance due to increasing levels of manmade RFI and operation outside the protected radio astronomy bands. The effect of RFI on astronomical data can be significantly reduced through real-time excision. In this paper, Median Absolute Deviation (MAD) is used for excising signals corrupted by strong impulsive interference. MAD estimation requires recursive median calculation which is a computationally challenging problem for real-time excision. This challenge is addressed by implementation of a histogram-based technique for MAD computation. The architecture is developed and optimized for Field Programmable Gate Array (FPGA) implementation. The design of a more robust variant of MAD called Median-of-MAD (MoM) is described. The architecture of MAD and MoM techniques and subsequent optimization allows for four RFI excision blocks on a single Xilinx Virtex-5 FPGA. These techniques have been tested on the GMRT wideband backend (GWB) processing a maximum of 400MHz bandwidth and the results show significant improvement in the signal-to-noise ratio (SNR).

Steganography has become one of the most significant techniques to conceal secret data in media files. This paper proposes a novel automated methodology of achieving two levels of security for videos, which comprise encryption and steganography techniques. The methodology enhances the security level of secret data without affecting the accuracy and capacity of the videos. In the first level, the secret data is encrypted based on Advanced Encryption Standard (AES) algorithm using Java language, which renders the data unreadable. In the second level, the encrypted data is concealed in the video frames (images) using FPGA hardware implementation that renders the data invisible. The steganographic technique used in this work is the least significant bit (LSB) method; a 1–1–0 LSB scheme is used to maintain significantly high frame imperceptibility. The video frames used as cover files are selected randomly by the randomization scheme developed in this work. The randomization method scatters the data throughout the video frames rendering the retrieval of the data in its original order, without a proper key, a challenging task. The experimental results of concealment of secret data in video frames are presented in this paper and compared with those of similar approaches. The performance in terms of area, power dissipation, and peak signal-to-noise ratio (PSNR) of the proposed method outperformed traditional approaches. Furthermore, it is demonstrated that the proposed method is capable of automatically embedding and extracting the secret data at two levels of security on video frames, with a 57.1dB average PSNR.

A highly secure communication method is essential for end users for the exchange of information which is not interpreted by an intruder. Cryptography plays a crucial role in the current and upcoming digital worlds, for secure data transmission in wired and wireless networks. Asymmetric and symmetric cryptographic algorithms encrypt data against vulnerable attacks and transfer to authenticated users. Steganography is a method for providing secure information with the help of a carrier file (text, video, audio, image, etc.). This paper proposes Deoxyribonucleic Acid (DNA)-based asymmetric algorithm which is used to encrypt the patient’s secret information and its performance is compared with ElGamal, RSA and Diffie–Hellman (DH) cryptographic algorithms. The proposed asymmetric algorithm is applied to image steganography which is used for encrypting and concealing the patient’s secret information in a cover image. The proposed method consumes less hardware resources with improved latency. Dynamic Partial Reconfiguration (DPR) allows to transform a selective area rather than complete shutdown of the entire system during bitstream configuration. Cryptosystem with DPR is designed, synthesized in Xilinx Vivado and simulated in Vivado simulator. The design is targeted at Basys3, Nexys4 DDR and Zync-7000 all-programmable SOC (AP SoC) architectures and programmed with secure partial bit files to avoid vulnerable attacks in the channel.

We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio interferometers.

The process to locate objects in an image passes through different phases. At the forefront of these phases, and most importantly, is the edge detection. If edges in an image are identified accurately, all of the objects will be located correctly for further processing phases. Noisy images contain high-frequency contents which might be interfered with image edges that makes edge detection more difficult. In this paper, a software comparative analysis of the performance of three different edge detectors, namely, Roberts, Prewitt and Sobel, is presented. The comparative analysis is performed to check the performance robustness of the edge detectors when noise level fluctuates in the image. In addition, an embedded hardware (HW) system is developed to implement the three detectors on the Zedboard FPGA prototyping board. The purpose of this implementation is to have an embedded system for on-the-move applications where portability is desired. To exploit the new features of the Xilinx Zynq-7000 series, we partition the implementation into (1) hardware part (running on logic gates of FPGA) and (2) software (SW) part (running on ARM processor of FPGA). This heterogeneous HW/SW implementation allows for high accurate results with high speed and efficient area. Furthermore, a hardware comparative analysis of the speed and area of the detectors is presented. The evaluation is performed by using different images (with their ground truths) downloaded from the BSDS500 dataset. The tools used for FPGA implementation are MATLAB and Microsoft Visual Studio (as software tools), Vivado High-level synthesis (HLS) and Software Development Kit (SDK) (as hardware tools). The experimental results show that the Roberts detector achieves better edge detection when the noise level is higher than 40%. It is also faster and requires less capacity of logic gates among the other detectors employed in this study.

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of $5M+4S+2D$ and $5M+4S+1D$ for general and special cases of BECs, respectively, where $M,S$ and $D$ denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields ${𝔽}_{2^{163}}$ and ${𝔽}_{2^{233}}$ are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement. Therefore, this work aims to propose an efficient implementation of the CSS method on Field-Programmable Gate Array (FPGA) to achieve the desired performance. Different parallelization and optimization techniques such as loop unrolling, loop pipelining, dataflow, and loop flattening are adopted and applied to explore the opportunities of any computation and storage that could be eliminated in order to achieve high efficiency. The results of the proposed optimized implementation achieve the highest performance compared with other related implementations.

This paper deals with a new modified hyperchaotic van der Pol–Duffing (MVPD) snap oscillator. Various dynamical properties of the proposed system are investigated with the help of Lyapunov exponents, stability analysis of the equilibrium points and bifurcation plots. The existence of the Hopf bifurcation is established by analyzing the corresponding characteristic equation. It is also proved that the MVPD oscillator shows multistability with coexisting attractors. Various numerical simulations are conducted and presented to show the dynamical behavior of the MVPD system. To show that the system is hardware realizable, we derive the discrete model of the MVPD system using the Euler’s method and using the hardware–software cosimulation, the proposed MVPD system is implemented in Field Programmable Gate Arrays. It is shown that the output of the digital implementations of the MVPD systems matches the numerical analysis.

This paper presents an implementation of Rivest, Shamir and Adleman (RSA) cryptosystem based on hardware/software (HW/SW) co-design. The main operation of RSA is the modular exponentiation (ME) which is performed by repeated modular multiplications (MMs). In this work, the right-to-left (R2L) algorithm is used for the implementation of the ME as a programmable system on chip (PSoC). The processor MicroBlaze of Xilinx is used for flexibility. The R2L method is often suggested to improve the timing performance, since it is based on parallel computations of MMs. However, if the optimization of HW resources is a constraint, this method can be executed sequentially using a single modular multiplier as a custom intellectual property (IP). Consequently, the execution time of the ME becomes dependent of three factors, namely the capability of the custom IP to perform the MMs, the nonzero bit string of the exponent and the communication link between the processor and the custom IP. In order to achieve the best trade-off between area, speed and flexibility, we propose three implementations in this work. The first one is a pure software solution. The second one takes benefit of a HW accelerator dedicated to the MM execution. The last one is based on a dual strategy. Two parallel MMs are implemented within a custom IP and local memories are used close to the arithmetic units to minimize the communication link influence. The results show that in the application to RSA 1024-bits, the ME runs in 22,25 ms, while using only 1,848 slices.

This paper proposed an adaptive neuro-fuzzy model (ANFIS) to multilevel inverter (MLI) for grid connected photovoltaic (PV) system. The purpose of the proposed controller is that it is not requiring any optimal pulse width modulated (PWM) switching-angle generator and proportional–integral controller. The proposed method strictly prohibits the variations present in the output voltage of the cascaded H-bridge MLI. In this method, the ANFIS have the input which is grid voltage, the difference voltage and the output target is control voltage. By using these parameters, the ANFIS makes the rules and has been tuned perfectly. During the testing time, the ANFIS gives the control voltage according to the different inputs. The resultant control voltage equivalent gate pulses are utilized for controlling the insulated gate bi-polar switches (IGBT) of MLI. Then the ANFIS based MLI for grid connected PV system is implemented in the MATLAB/simulink platform and the effectiveness of the proposed control technique is analyzed by comparing with the neural network (NN), fuzzy logic control, etc. The comparison results demonstrate the superiority of the proposed approach and confirm its potential to solve the problem. A prototype of three-phase grid connected cascaded H-bridge inverter has been developed using field-programmable gate array (FPGA) and results are analyzed.

This work presents a novel technique for a high-speed implementation of the newly selected cryptographic hash function, Secure Hash Algorithm-3 (SHA-3) on Xilinx’s Virtex-5 and Virtex-6 Field Programmable Gate Arrays (FPGAs). The proposed technique consists of a two-phase implementation approach. In the first phase, all steps of the SHA-3 core are logically combined, which helps to eliminate the intermediate states of core function, these states utilize more area and also slow the execution. The second phase deals with the hardware implementation of the first phase equations using Xilinx Look-Up-Table (LUT) primitives. This two phase implementation technique results in a throughput of 19.241Gbps on a Virtex-6 FPGA; this is the highest reported throughput to date for an FPGA implementation of SHA-3. This high throughput makes this technique ideally suited for the provision of Bump In The Wire (BITW) security for Internet of Things (IoT) applications.

The VHDL design and Field Programmable Gate Array (FPGA) implementation of a fuzzy control system to control the blood glucose level continuously based on current and previous values are presented. The design is based on simple models of the dynamic behavior of the glucose insulin system suitable for real-time control. The system is successfully implemented on FPGA promising efficient hardware implementation to be included in a low power, robust and reliable closed loop health monitoring system.

Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over $GF(2^{163})$ and $GF(2^{233})$ using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions.