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A digital controller for LED driver is presented. The controller is used in the flyback converter which works in discontinuous current mode (DCM). A comparator is adopted to shape the auxiliary winding voltage based on traditional primary side regulation (PSR). A five-states finite state machine (FSM) is designed to deal with the shaped auxiliary winding signal. The FSM extracts the system time information from the shaped signal and controls all the sequences in the whole system. To achieve high accuracy of the output current, an adaptive delay compensation scheme is adopted. A LED prototype whose typical output power is 7 W is used in both simulation and experiment to demonstrate the effectiveness of this novel digital controller. The measurement results show that the line regulation when the input ac voltage varies from 85–265 V is 3.4% and the load regulation when the load varies from 3–10 LEDs is 2.5%.

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.

Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gating (CG) has been proposed for finite state machines (FSMs). The CG logic is based on the idea of dynamically disabling the clock signal to the sequential blocks of the FSM during periods of inactivity. The inactive state is decided by the occurrence of self-loops within the FSM. The proposed gating technique operates at a fine level of granularity and can be generally implemented to any FSMs. A technique of partitioning the registers of the FSM is introduced in this work in order to avoid functional errors and signal losses during gating. The logic of registers partitioning for CG in large FSMs containing few or no self-loops is also presented in this work. The simulation results obtained shows up to 38% (max) dynamic power reduction of the FSM with a little penalty in area. The timing slack associated with the gated and non-gated FSMs is also analyzed for varying clock frequencies. The results indicate a minimal increase in delay after gating. The technique for CG in large FSMs containing few or no self-loops has yield up to 58% (max) power reduction.

This paper proposes a Finite State Machine (FSM) testing technique based on deep neural network (DNN). This technique verifies the correctness of an implementation FSM-B of a specification FSM-A. Using the back-propagation algorithm, a deep neural network is trained with the input–output patterns for a given set of transition functions that specify an FSM. Initially, for FSM-A, the input patterns and the corresponding output patterns (I/O pairs) are generated. Then most of the patterns are used to train the DNN. Once the training is over, the DNN is validated with the remaining I/O pairs (around 20%). The model can be used for verifying the correctness of FSM-B after training and validation of the DNN. Some inputs are applied to FSM-B and the generated output patterns are compared with the predicted values of the proposed DNN. The difference of accuracy percentages between FSM-A and FSM-B is recorded and zero difference between them indicates the fault-free condition of the implementation FSM-B. To check the effectiveness of the scheme, the output- and state-type faults are injected to derive mutant FSMs. Experimental results performed on the MCNC FSM benchmarks prove the efficacy of the proposed method. Only a few numbers of tests are needed to detect the presence of anomaly, if any. Hence, the test time reduces significantly — resulting in an average test time reduction of 85.67% compared to the conventional techniques. To the best of our knowledge, for the first time a DNN-driven testing scheme is being proposed.

ISO 14143-1 specifies that a functional size measurement (FSM) method must provide measurement procedures to quantify the functional user requirements (FURs) of software. Such quantitative information, functional size, is typically used, for instance, in software estimation. One of the international standards for FSM is the COSMIC FSM method — ISO 19761 — which was designed to be applied both to the business application (BA) software domain and to the real-time software domain. A recurrent problem in FSM is the availability and quality of the inputs required for measurement purposes; that is, well documented FURs. Business process (BP) models, as they are commonly used to gather requirements from the early stages of a project, could be a valuable source of information for FSM. In a previous article, the feasibility of such an approach for the BA domain was analyzed using the Qualigram BP modeling notation. This paper complements that work by: (1) analyzing the use of BPMN for FSM in the BA domain; (2) presenting notation-independent guidelines for the BA domain; and (3) analyzing the possibility of using BP models to perform FSM in the real-time domain. The measurement results obtained from BP models are compared with those of previous FSM case studies.

This paper compares three finite element models for determining the buckling and post-buckling performance of infinite length thin walled composite and metal stiffened panels — such as for modeling theoretical aircraft upper wing skin panels — namely single bay, double half-bay and quad half-bay models. The quad half-bay model is shown to be the ideal model as all wavelengths of buckling are permitted. This model gives an accurate estimate of postbuckling behavior that can include advanced behavior such as mode jumping or collapse while the single bay and double half-bay models are more restrictive and do not allow for accurate mode jumping to take place. Sample panels are analyzed for buckling performance using the computer program VICONOPT, which assumes an infinite length structure based on exact strip theory. This analysis is then compared to results from the quad half-bay FEM model, using the Abaqus solver, where the two models are in good agreement for the initial buckling performance for both the metal and composite panels. Buckling prediction for the quad half-bay model is within $0.5\%$ for the critical buckling mode, and within $3\%$ of all compared modes; and postbuckling performance compares well with the results of previous investigation of the same sample panel geometry.

This paper presents a Finite State Machine (FSM) implementation method based on symbolic functional decomposition. This novel approach to multilevel logic synthesis of FSMs targets Field Programmable Gate Array (FPGA) architectures. Traditional methods consist of two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However, none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper, the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementation in FPGA architectures. The symbolic functional decomposition does not require a separate encoding step. It accepts FSM description with symbolic states and performs decomposition, producing such a state encoding that guarantees the optimal or near-optimal solution.

A new methodology for finding hybrid RANS/LES damping functions is proposed. The Flow Simulation Methodology framework is modified from Speziale's original formulation [AIAA 36,173 1998] to allow for fewer grid points away from solid boundaries. The proposed functional form is regressed using an evolutionary algorithm. The solution is trained by considering DNS data of a separated flow. This sophisticated approach to building the damping function allows for the development of a hybrid methodology adaptable to any level of required modelling. The regressed model is compared to highly resolved reference LES on the classical two dimensional periodic hills case, for which the agreement is very good.