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Floating-body-induced transient mechanism in advanced FinFETs was investigated for unified and multi-bit memory capability. Nonvolatile memory operation was achieved by modifying the SOI buried insulator (BOX) such as the SiO₂-Si₃N₄-SiO₂ (ONO) BOX can accumulate permanent charges. Charges are injected/removed in the Si₃N₄ layer by back-gate or drain bias and sensed remotely, by gate coupling, through the modulation of the drain current flowing at the front interface. On the other hand, the isolated silicon body of the transistor can store volatile charges, generated by impact ionization and able to modulate the drain current flowing at the back interface. Our experimental results successfully demonstrate that these two different memory modes can be advantageously combined for multi-bit volatile memory operation. The volatile memory behavior strongly depends on the distribution of the nonvolatile charges stored in the nitride buried layer. Our measurements manifest that the nonvolatile charges located near the drain terminal have larger influence on the volatile memory operation than the charges located at the opposite terminal. Also, we reveal that the bias conditions and device geometry are important factors for the two memory modes.

At 7nm technology node, the trigate FinFETs are the promising candidates for modern integrated circuits. Their optimal design and improved performance are key demands for most of the leading semiconductor manufacturing industries. This work proposes an improvement of electrical performance through process induced stress optimization for a compressively stressed FinFET at a 7nm Technology node. The variation of two design parameters (fin angle and epi angle) can lead to a change in stress and hence the devices’ electrical performance, which is the major focus of this study. A process induced compressively stressed p-channel FinFET at 7nm Technology node is virtually fabricated using Technology CAD (TCAD) by introducing a SiGe epitaxial layer at Source and Drain regions. The variation of electrical performances with change in epi angle (θ_Epi) and fin angle (θ_Fin) is critically analyzed. These results predict the improvement of the drive current and reduction in short channel effect with the appropriate selection of the θ_Fin and θ_Epi. Hence, the predictive TCAD simulations explored the new avenues of strain-engineered FinFET for future CMOS technology generations.

Floating-body-induced transient mechanism in advanced FinFETs was investigated for unified and multi-bit memory capability. Nonvolatile memory operation was achieved by modifying the SOI buried insulator (BOX) such as the SiO₂-Si₃N₄-SiO₂ (ONO) BOX can accumulate permanent charges. Charges are injected/removed in the Si₃N₄ layer by back-gate or drain bias and sensed remotely, by gate coupling, through the modulation of the drain current flowing at the front interface. On the other hand, the isolated silicon body of the transistor can store volatile charges, generated by impact ionization and able to modulate the drain current flowing at the back interface. Our experimental results successfully demonstrate that these two different memory modes can be advantageously combined for multi-bit volatile memory operation. The volatile memory behavior strongly depends on the distribution of the nonvolatile charges stored in the nitride buried layer. Our measurements manifest that the nonvolatile charges located near the drain terminal have larger influence on the volatile memory operation than the charges located at the opposite terminal. Also, we reveal that the bias conditions and device geometry are important factors for the two memory modes.