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This paper investigates temperature evolution in graphene field-effect transistors. We present a refined Ballistic-diffusive equation model (BDE) tailored for scrutinizing the phonon transport within GNRFET transistors. Furthermore, we examine the influence of the channel length on thermal characteristics. COMSOL Multiphysics is employed to compute the phonon transport and temperature distribution in nano-GNRFET. Our results reveal that the phonon transport anticipated by the suggested BDE model closely corresponds to that derived from the Boltzmann transport equation. The proposed model proficiently gauges the thermal performance of GNRFET, with the outcomes suggesting that the characteristic length of the GNR has a negligible impact on the temperature increase.

The effect of channel uniaxial strain on thermal conductivity of graphene nano-ribbon field effect transistor (GNRFET) is analyzed by self-consistent Hückel method. The supposed strains are tensile and its values are 2% to 24% of lattice constant. All of the assumed strains are applied to the channel length direction. Energy band gap, density of states (DOS), phonon transmission, thermal conductivity, and I–V characteristics of the GNRFET have been calculated. The results show that by increasing the strain, the energy band gap of the channel is increased and the drain current is decreased. Also by increasing the band gap, phonon transmission is decreased. Maximum phonon transmission occurs in 8% strain. By considering all of these parameters, the results show that there is a maximum thermal conductivity versus temperature in 8% uniaxial strain that is more than the bare one and its value is decreased intensively in 16% and 24% strain. This is due to maximum phonon transmission that is observed in 8% strain and increasing the DOS around the energy band gap in this value. Also, it is observed that in the energy range of more than 0.75 eV, by increasing the strain, thermal conductivity is increased.

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16nm MOS-GNRFET model.

This paper investigates temperature evolution in graphene field-effect transistors. We present a refined Ballistic-diffusive equation model (BDE) tailored for scrutinizing the phonon transport within GNRFET transistors. Furthermore, we examine the influence of the channel length on thermal characteristics. COMSOL Multiphysics is employed to compute the phonon transport and temperature distribution in nano-GNRFET. Our results reveal that the phonon transport anticipated by the suggested BDE model closely corresponds to that derived from the Boltzmann transport equation. The proposed model proficiently gauges the thermal performance of GNRFET, with the outcomes suggesting that the characteristic length of the GNR has a negligible impact on the temperature increase.