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As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, $g_m$-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based $g_m$-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a $12\times$ power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 $\mu$W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

This paper represents a new enhanced Colpitts oscillator, which is designed based on g_m-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, the differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using 0.18 μm technology and is simulated under 1.8 V supply voltage in advanced design system (ADS). Simulations show the output phase noise of -140 dBc/Hz at 1 MHz offset frequency when the operating frequency is 1 GHz.

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode g_m-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4MHz and 132dB, respectively. The amplifier is operated at 0.6V dual supply with 89$\mu$W power consumption and has a nearly symmetrical average slew rate of 51.5V/$\mu$s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.