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This paper describes a tabu search approach for a multiprocessor scheduling problem, where a list of jobs has to be scheduled on identical parallel processors. Each job in the list has a release date, a due date, a processing time and a set of predecessors. The objective is to minimize the number of processors used while respecting the constraints imposed by release dates, due dates and precedences. Two versions of this problem are considered here, in the first one precedence constraints are relaxed, they are taken into account in the second one. The proposed method is used to solve High Level Synthesis problem instances. The results show the effectiveness of our approach for both versions of the problem. A comparison with an exact method is also conducted.

The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an ∊-approximate solution in polynomial time where ∊ is a user defined parameter. The algorithm probably generates solutions that differ at-most ∊C_max from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.

Hardware binding is an important step in high level synthesis (HLS). The quality of hardware binding affects the area-time efficiency of a design. The goal of a synthesis process is to produce a design which meets the area-time requirements. In this paper, we present a new hardware binding algorithm with focus on area reduction. It is called extended compatibility path-based (ECPB) hardware binding and extends the compatibility path-based (CPB) hardware binding method by exploiting inter-operation flow dependencies, non-overlapping lifetimes of variables and modifying the weight relation in order to make it application aware and thus adaptive in nature. The presented methodology also takes into account bit width of functional units (FUs) and multi mode FUs. It performs simultaneous FU and register binding. Implemented within a C to register transfer level (RTL) framework, it produces binding results which are better than those produced by weighted bipartite matching (WBM) and CPB algorithms. The use of ECPB algorithm results in an average reduction of 34% and 17.44% in area-time product over WBM and CPB methods, respectively.

System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, $10\times$ improvement in speed and $4\times$ improvement in hypervolume.

In past years, software used to be the main concern of computer security, and the hardware was assumed to be safe. However, Hardware Trojans, which are a malicious alteration to the circuit, pose a threat to the security of a system. Trojans may be distributed across different components of the system and can bring down the security by communicating with each other. Redundancy and vendor diversity-based methods exist to detect Hardware Trojans, but with an increase in the hardware overhead. This work proposes a novel vendor allocation procedure to reduce the hardware cost that comes with Trojan detection methods. To further reduce the cost by minimizing resource requirements, an evolutionary algorithm-based Design Space Exploration methodology is proposed with options for loop unrolling and operation chaining. For reducing the cost of hardware Trojan detection and isolation, the proposed algorithm extends an existing implementation of Firefly algorithm. The proposed method is compared with the existing algorithms, using cost-based and Pareto-based evaluations. The results obtained demonstrate the ability of the new algorithm in achieving better solutions with a 77% reduction in cost when compared to the previous solutions.