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There is an increasing demand for biometric security systems in several fields. This study presents a highly accurate facial recognition method that uses high-speed transformation and facial morphing using region-limited log-polar transformation based on a center point calculated from the coordinates of both eyes and corners of the mouth. Log-polar transformation is limited to the region, so that the region including the feature can be suppressed to the minimum range, thereby facilitating high-speed transformation. Additionally, after facial morphing, the shapes of the eyes and mouth are altered based on the outline of the face, enabling high-precision facial recognition. The efficacy of the proposed method is verified experimentally. Therefore, we can confirm that 91.72% of images using the color FERET database and 96% of images using the FEI face database can be recognized using our method.

This paper presents a new high speed voltage-mode MAX–MIN method for fuzzy applications. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100 MHz.

In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm². By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180nm CMOS process and occupies a small area of 0.048mm² excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of $\pm$1.5${}^{\circ }$C from $-$45${}^{\circ }$C to 85${}^{\circ }$C under a supply voltage of 1.4–2.4V showing a worst-case supply sensitivity of 0.5${}^{\circ }$C/V. The sensor maintains a high conversion rate of 45KS/s with a fine resolution of 0.25${}^{\circ }$C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8V, the maximum energy consumption per conversion is only 7.8nJ at $-$45${}^{\circ }$C.

A new design technique is proposed and discussed for the design of active load using the bulk-driven method. The proposed method uses gate-driven input drivers with bulk-driven MOS load. Further, it is used to design single stage amplifiers, such as common source (CS) and common gate (CG). In addition to the proposed technique, a very efficient method is implemented to improve and control the gain of the amplifiers, which is named as Gain Control by Bulk Amplification (GACOBA) Technique. The large signal, small signal and frequency domain analysis of proposed designs are done and to verify the outcomes it is simulated in SPECTER at 0.7V supply with 45nm CMOS technology. The result shows that the transconductance and gain of proposed single stage CS amplifier are increased without affecting impedance seen by output node. On the other hand, GACOBA technique is useful for gain enhancement in CS and CG amplifier.

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45nm and 180nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45nm result shows that the comparator has the total delay as low as 104.3ps and consumes only 0.288fJ of energy per conversion from a 0.8V supply. The mean value of input voltage error due to kickback noise is found as 306nV.

This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5GHz of maximum frequency with 1.9mW power consumption. The divider is implemented in 0.18$\mu$m CMOS technology with 1.8V power supply.

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.

The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C²P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C²N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C²P-C²N, DMR-C²P and DMR-C²N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C²N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature.

The increasing demand for low voltage, power efficient, high-speed analog-to-digital converters (ADCs) results in the improvement of speed and power of regenerative dynamic comparator. In this paper, a dual-tail dynamic comparator is used with two extra transistors in the latch stage. These extra transistors help in the increase of transconductance of the latch stage, which helps decrease the delay of the proposed comparator. Mathematical analysis is done for the proposed architecture; this gives the idea of reducing the delay of the comparator with an increase in the transconductance of the comparator. The simulation and layout of the proposed comparator are done on the Cadence software with 90nm CMOS technology. This proposed design is simulated with a 2GHz clock frequency at supply voltage of 1V. The proposed architecture consumes a power of 39.19$\mu$W and a delay of 143.12ps at 1V supply voltage, 5mV input difference voltage and 0.9V common mode voltage. The Monte Carlo simulation of the proposed architecture for power, delay, power delay product (PDP) and offset is also demonstrated in this paper. Process corner analysis is done for power, delay and PDP.

Nonlinear processes in quantum well infrared photodetectors (QWIP) are reviewed. Being an intersubband dipole transition based photoconductor, the nonlinear behaviors in QWIPs are caused by both the (extrinsic) photoconductive transport mechanism and (intrinsic) nonlinear optical processes. Extrinsic nonlinearity leads to a degradation of QWIP performance at high incident power or low operating temperatures. Some intrinsic nonlinear QWIP properties are useful in applications, such as in autocorrelation of short pulses by two-photon absorption. The general area of QWIP nonlinear properties has not been extensively investigated. We point out some directions for further studies and hope to stimulate more research activities.

A laboratory centrifuge is a piece of laboratory equipment, driven by a motor, which spins liquid samples at high speed. There are various types of centrifuges, depending on the size and the sample capacity. Like all other centrifuges, laboratory centrifuges work by the sedimentation principle, where the centripetal acceleration is used to separate substances of greater and lesser density. The information for synthesizing the molecules that allow organisms to survive and replicate is encoded in genomic DNA. Extracted and purified genomic DNA is very important for the analysis of single nucleotide polymorphisms (SNPs), disease states, and for many other multiplex and real-time PCR applications. The aim of this work is to design a genomic DNA extraction system that satisfies downstream application needs necessary for the successful completion of experiments and able to isolate a purified genomic DNA from many sources from bacteria to humans and also is able to encompass tissues from blood to muscle and from leaf to seed. Results revealed that the proposed system works with high efficiency and spins at up to 12,000 RPM to facilitate separation of the different phases of the extraction.

The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

An analytical method is presented for determination of vibration characteristics of high speed Double-Segment Compound Rotating disks. More specifically, a systematic approach based on established solution for linear in-plane vibration of each segment satisfying the displacement and stresses compatibility is developed. Fixed and free boundary conditions for the compound spinning annular disks are considered, and natural frequencies and mode shapes of rotating the disks are computed. The medium for each segment is considered to be homogenous, isotropic, and elastic. The developed analytical solution was achieved by implementing two-dimensional plane stress theory. The modal displacements and stresses at both inner and outer boundaries are determined. The dimensionless natural frequencies for different modes, rotating speeds, and thickness ratios are computed. The effect of stiffness changes for each segment on the natural frequencies are also studied.