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Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

With the increasing requirements of transmitting larger amounts of diverse video and image data, the PCI express (PCIe) interface has been extensively used in high-speed digital systems for multimedia processing and communication. However, the existing PCIe transmission methods are not efficient to transmit multi-channel videos on FPGA processors, as they waste PCIe bandwidth and hardware resources. In this paper, an efficient PCIe transmission method for multi-channel video is presented on an FPGA processor. First, to reduce the programmed I/O (PIO) write latency, the command caching method is adopted. The traditional DMA descriptors are transformed into DMA commands, which are smaller, and the command buffer is used to store these commands. Second, a dynamic splicing mechanism is proposed for data transmission and commands the scheduling separately. The multi-type data is transmitted concurrently in this dynamic splicing mechanism. Moreover, the adjacent commands are spliced into one command, which reduces the DMA initiation times. Finally, the direct kernel memory access technique and timer self-feedback monitor technique are applied to improve the transmission efficiency and enhance the system reliability. The experimental results show that the transmission efficiency of the proposed method is increased by nearly 30% compared with other conventional methods, and the highest measured transfer rate is 1631 Mbytes/s on write and 1582 Mbytes/s on read, which reaches 84.4% of the theoretical maximum.

The Linux Unified Key Setup (LUKS) is the standard key management scheme for the full disk encryption solution implemented in Linux-based operating systems. It is composed of PBKDF2, an anti-forensic splitter, and a cipher. In this paper, a new FPGA-based high-throughput and pipelined implementation of LUKS is presented. We design a four-stage pipelined SHA-1 module without the multiplexers between piecewise function and a total eight-stage pipelined PBKDF2 by reusing two hash results. Besides, we implement ST box-based AES decipher with BRAM resources, which improves the performance and leaves most of the slice resources to PBKDF2 architecture. By using the above techniques, we instantiate a high throughput LUKS co-processor in a Xilinx Zynq 7030 FPGA. Compared to the previous work of implementation of LUKS PBKDF2 with AES on FPGA, our design shows better improvement of the speed and efficiency by 16 times and 8 times, respectively. Our speed of LUKS key recovery is even faster than Nvidia GPU GTX480.

In this paper, we present a fully pipelined and semi-parallel channel convolutional neural network hardware accelerator structure. This structure can trade off the compute time and the hardware utilization, allowing the accelerator to be layer pipelined without the need for fully parallelizing the input and output channels. A parallel strategy is applied to reduce the time gap in transferring the output results between different layers. The parallelism can be decided based on the hardware resources on the target FPGA. We use this structure to implement a binary ResNet18 based on the neural architecture search strategy, which can increase the accuracy of manually designed binary convolutional neural networks. Our optimized binary ResNet18 can achieve a Top-1 accuracy of 60.5% on the ImageNet dataset. We deploy this ResNet18 hardware implementation on an Alphadata 9H7 FPGA, connected with an OpenCAPI interface, to demonstrate the hardware capabilities. Depending on the amount of parallelism used, the latency can range from 1.12 to 6.33 ms, with a corresponding throughput of 4.56 to 0.71 TOPS for different hardware utilization, with a 200 MHz clock frequency. Our best latency is $8\times$ lower and our best throughput is $1.9\times$ higher compared to the best previous works. The code for our implementation is open-source and publicly available on GitHub at https://github.com/MFJI/NASBRESNET.

In this paper, a high-throughput droplet method is presented for screening corrosion inhibitors, particularly for those metals that are subjected to pitting. To this objective, AA5083 was used as a case study as it is subject to pitting corrosion in saline solution containing different corrosion inhibitors. This paper outlines how critical parameters are measured and calculated (average pit depth and maximum pit depth) and the errors and consistency of the method, and the definition of corrosion inhibition via the method. The results from this method were then compared to the results of inhibition efficiency derived from potentiodynamic polarization scans for inhibitors with a range of performance. The method was conducted at temperature $T=22\pm 2^{\circ }$C inside a humidity chamber, and concentration 10${}^{-3}$ M of seven chemical compounds that have similarities in their structures. The discrepancies were profound for the cases where the inhibitor was of low efficiency, which is ascribed to the fact that these pits’ growth is dominated by that of a few large pits.

The core philosophy of Materials Genome Initiative (MGI) is the transition of the way of new materials design from the traditional “trial-and-error” approach to the in-silico materials design approach which employs intensive computing and material informatics. In June 2011, President Barack Obama launched MGI alongside the Advanced Manufacturing Partnership to help businesses discover, develop and deploy new materials twice as fast. In this paper, the concept of rare and precious genome is presented first, followed by the progress of MGI. After that, we focus on the research status of the rare and precious metals’ MGI including the computational tools, the high-throughput experimental methodologies and the rare and precious metals database. We also introduce the application of MGI in the development of rare and precious metal materials, outline the remaining fundamental challenges and present an outlook on the future of the rare and precious metals’ MGI.

Proteomics has become a powerful technique to investigate cellular processes and network functions. This became possible as a result of major progress in the sensitivity of mass spectrometry instrumentation and data analysis software. As proteomics technologies are now becoming available to the wider scientific community, efforts are under way to identify complete proteomes. This information is used to improve genome annotation and to identify and confirm protein splice variants. Analysis of protein modifications and protein variants uses novel scoring and prediction tools independent of established protein databases. We discuss the proteomics tools and analysis pipelines that can be applied to rice in order to facilitate our understanding of rice genome structure and function.