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Aqueous zinc-ion batteries (ZIBs) have shown great potential in large-scale energy storage systems due to their economic efficiency and environmental friendliness. However, cathodes for aqueous ZIBs are affected by the slow Zn${}^{2+}$ diffusion kinetics and limited capacity. Herein, Mg${}_{0.17}$V₂O${}_5\cdot 1.7$H₂O (MgVO) nanobelt cathode with a large interlayer spacing of 13.0 Å is prepared via a one-step hydrothermal approach. Furthermore, the pre-intercalated Mg${}^{2+}$ can stabilize the crystal structure and prevent Zn${}^{2+}$ from being trapped in the lattice. As a result, MgVO cathode delivers a high capacity of 386 mAh g${}^{-1}$ at 0.1 A g${}^{-1}$, and impressive long-term cycling stability with a capacity retention of 91% after 1500 cycles at 5 A g${}^{-1}$. Moreover, the Zn//MgVO battery can provide a high-energy density of 269 W h kg${}^{-1}$ at 0.1 A g${}^{-1}$ and a high-power density of 2701 W kg${}^{-1}$ at 5 A g${}^{-1}$. The simple preparation and low cost make this cathode show great potential in the applications of large-scale energy storage.

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are k times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping. Moreover, the area and power consumption of this scheme is less than full-associative scheme.

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (Design1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most efficient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results confirm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the most important concerns of nanoelectronics is studied using Monte Carlo transient analysis. This simulation reveals that Design3 functions very well against manufacturing process variations.

Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss.

Di(4-bromophenyl)ketone and various aromatic diamines as the monomers, a series of novel poly(imino ketone)s (PIKs) have been synthesized via palladium-catalyzed aryl amination, which is Hartwig-Buchwald polycondensation reaction. The structures of PIKs are characterized by means of elemental analysis, FT-IR, ¹H-NMR and UV-Vis spectroscopy. The results show a good agreement with the proposed structure. The general properties of PIKs are studied by DSC, TG and wide-angle X-ray diffraction, the solubility behavior is measured at polymer concentration 5 mg·mL^-1. It is obvious that PIKs show high glass transition temperature (T_g > 220°C), good thermal stability with high decomposition temperatures (T_D > 480°C) and excellent solubility.