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A closed-loop high-precision front-end interface circuit in a standard 0.35 $\mu$m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 $\mu$m CMOS process and the active circuit area is about $4.6\times 3.7{\mathrm{\text{mm}}}^2$. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of $16.7\mathrm{\text{nV}}/{\mathrm{\text{Hz}}}^{1/2}$. The ripple can be suppressed to less than 10 $\mu$V by ripple suppression loop.

This paper presented a high-precision, ultra-low-power hysteretic voltage detector (HVD) using current comparison to detect voltage default crossing moments for energy-harvesting systems (EHS) in wireless sensor network (WSN) applications. The HVD mainly consists of four parts: a specially designed voltage-to-current converter (VCC) with thermal stability improvement, a comparison core to make current-based comparison, a current pre-amplifier to improve its transient performance and a Schmitt inverter to provide the hysteresis characteristic. The prototype of this HVD has been implemented in SMIC 0.18 μm CMOS process and occupies 0.036 mm² area without pads. The hysteresis window is about 120 mV wide. The temperature coefficient (TC) is about -170.2 ppm°C. The average variation to different process corners can be reduced to 1.4% by MOSFET and resistor trimming. The total power consumption is only 701.5 nW when VDD is around 1.8 V.

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18$\mu$m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of $-$87.23dB and spurious-free dynamic range (SFDR) of 88.14dB for a 1MHz sinusoidal input of 800mV peak-to-peak amplitude at 50MHz sampling rate with a 1.8V supply voltage.

Traditional electronic load has some deficiencies such as low accuracy, low dynamic range, and low intelligence, etc. In order to overcome these issues, this paper is introducing a high-power and high-precision electronic load system, proposing a solution for further combining the high-power and the high-precision, developing a user-computer interface based on a virtual instrument technology, and an embedded programming for the testing system. The electronic load system is designed based on LabView, single chip microcomputer and MOSFET that ensure high testing accuracy, large dynamic range and secondary development function.

This article has reviewed the development of embedded system, and sketched the system composition and working principle of digital quadrant. According to the current digital quadrant research, design methods about improving measurement precision and reducing the power consumption of the system are summarized, and its future development were discussed.