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In this paper, we present the design and implementation of a source-to-source High Performance Fortran assistant Tool (HPFT) in DEC 3000 workstations. For a given sequential program written in Fortran 77, the HPFT generates a vectorized, reuse-exploited and/or parallelized version for vector computers. Several new compilation schemes in vectorization, reuse exploitation and multithreading are designed in the HPFT. A performance evaluator is developed for measuring the system performance. The user interface is also designed for the programmer to capture the information related to the compilation and execution of the program. Experimental results based on the Convex C3840 vector computer show that the developed HPFT enhances the system performance and usually reduces the program execution time.

We present a novel, compile-time method for determining the cache performance of the loop nests in a program. The cache hit-rates are produced by applying the reference string, determined during compilation, to an architecturally parameterized cache simulator. We also describe a heuristic that uses this method for compile-time optimization of loop ranges in iteration-space blocking. The results of the loop program optimizations are presented for different parallel program benchmarks and various processor architectures, such as IBM SP1 RS/6000, the SuperSPARC, and the Intel 1860.

Tiling has been used by parallelizing compilers to define fine-grain parallel tasks and to optimize cache performance. In this paper we present a novel compile-time technique, called miss-driven cache simulation, for determining loop tile sizes that achieve the highest cache hit-rate. The widening disparity between a processor's peak instruction rate and main memory access time in modern computer systems makes this kind of optimization increasingly important for overall program efficiency.

Our simulation technique generates only those references of a loop nest that may generate a cache memory miss and processes them on an architecturally accurate cache model at compile-time. Processing only a small portion of the memory reference trace of a program yields simulation speeds in the millions of memory references per second on workstations, with statistics of misses per reference and inter-reference interference counts gathered at the same time. These simulation speeds and statistics allow for the accurate analysis of the impact of cache optimizations at compile-time.

We discuss the results of applying this method to guide loop tiling for such commonly used computational kernels as matrix multiplication and Jacobi iteration for various cache parameters.

This paper proposes a DSP fault tolerant approach based on loop optimization known as DSP Loop Optimization Approach (DLOA). DLOA reduces the performance overhead incurred by traditional fault tolerance techniques while maintaining their fault tolerance capabilities. DLOA delays the fault tolerance latency between errors detecting and errors handling to scheduling the software pipeline, increasing performance significantly. The performance experiments and the ion irradiation experiments in the Heavy Ion Research Facility in Lanzhou (HIRFL) demonstrated that DLOA used in SWIFT achieved a 6.2 times average speedup and with its fault tolerance ability unaffected.